2006 International Conference on Parallel Architectures and Compilation Techniques (PACT) (2006)
Seattle, WA, USA
Sept. 16, 2006 to Sept. 20, 2006
DOI Bookmark: http://doi.ieeecomputersociety.org/
Qingda Lu , Dept. of Computer Science and Engineering, The Ohio State University, Columbus, OH, USA
Sriram Krishnamoorthy , Dept. of Computer Science and Engineering, The Ohio State University, Columbus, OH, USA
P. Sadayappan , Dept. of Computer Science and Engineering, The Ohio State University, Columbus, OH, USA
Matrix transposition is an important kernel used in many applications. Even though its optimization has been the subject of many studies, an optimization procedure that targets the characteristics of current processor architectures has not been developed. In this paper, we develop an integrated optimization framework that addresses a number of issues, including tiling for the memory hierarchy, effective handling of memory misalignment, utilizing memory subsystem characteristics, and the exploitation of the parallelism provided by the vector instruction sets in current processors. A judicious combination of analytical and empirical approaches is used to determine the most appropriate optimizations. The absence of problem information until execution time is handled by generating multiple versions of the code — the best version is chosen at runtime, with assistance from minimal-overhead inspectors. The approach highlights aspects of empirical optimization that are important for similar computations with little temporal reuse. Experimental results on PowerPC G5 and Intel Pentium 4 demonstrate the effectiveness of the developed framework.
tiling, SIMD, bandwidth-limited, conflict misses, empirical search, matrix transposition, spatial locality
Q. Lu, S. Krishnamoorthy and P. Sadayappan, "Combining analytical and empirical approaches in tuning matrix transposition," 2006 International Conference on Parallel Architectures and Compilation Techniques (PACT), Seattle, WA, USA, 2006, pp. 233-242.