2006 International Conference on Parallel Architectures and Compilation Techniques (PACT) (2006)
Seattle, WA, USA
Sept. 16, 2006 to Sept. 20, 2006
DOI Bookmark: http://doi.ieeecomputersociety.org/
Rakesh Kumar , Dept of Computer Science and Engineering, University of California, San Diego La Jolla, CA 92093-0404
Dean M. Tullsen , Dept of Computer Science and Engineering, University of California, San Diego La Jolla, CA 92093-0404
Norman P. Jouppi , HP Labs, 1501 Page Mill Road, Palo Alto, CA 94304
Previous studies have demonstrated the advantages of single-ISA heterogeneous multi-core architectures for power and performance. However, none of those studies examined how to design such a processor; instead, they started with an assumed combination of pre-existing cores. This work assumes the flexibility to design a multi-core architecture from the ground up and seeks to address the following question: what should be the characteristics of the cores for a heterogeneous multi-processor for the highest area or power efficiency? The study is done for varying degrees of thread-level parallelism and for different area and power budgets. The most efficient chip multiprocessors are shown to be heterogeneous, with each core customized to a different subset of application characteristics — no single core is necessarily well suited to all applications. The performance ordering of cores on such processors is different for different applications; there is only a partial ordering among cores in terms of resources and complexity. This methodology produces performance gains as high as 40%. The performance improvements come with the added cost of customization.
multi-core architectures, heterogeneous chip multiprocessors, computer architecture
R. Kumar, D. M. Tullsen and N. P. Jouppi, "Core architecture optimization for heterogeneous chip multiprocessors," 2006 International Conference on Parallel Architectures and Compilation Techniques (PACT), Seattle, WA, USA, 2006, pp. 23-32.