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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2005)
St. Louis, Missouri
Sept. 17, 2005 to Sept. 21, 2005
ISSN: 1089-795X
ISBN: 0-7695-2429-X
TABLE OF CONTENTS
Introduction
Introduction

Committees (PDF)

pp. xii-xiii
Keynote Address
PROFILING

null (PDF)

pp. null

Variational Path Profiling (Abstract)

Brad Calder , Microsoft Corporation
Erez Perelman , Department of Computer Science and Engineering, University of California, San Diego
Trishul Chilimbi , Department of Computer Science and Engineering, University of California, San Diego
pp. 7-16

Extended Whole Program Paths (Abstract)

Sriraman Tallam , The University of Arizona Department of Computer Science
Xiangyu Zhang , The University of Arizona Department of Computer Science
Rajiv Gupta , The University of Arizona Department of Computer Science
pp. 17-26

Instruction Based Memory Distance Analysis and its Application (Abstract)

Soner Onder , Department of Computer Science Michigan Technological University
Zhenlin Wang , Department of Computer Science Michigan Technological University
Steve Carr , Department of Computer Science Michigan Technological University
Changpeng Fang , Department of Computer Science Michigan Technological University
pp. 27-37

HPS: Hybrid Profiling Support (Abstract)

Hussam Mousa , Computer Science Department University of California, Santa Barbara
Chandra Krintz , Computer Science Department University of California, Santa Barbara
pp. 38-50
CMPs AND CONSISTENCY

null (PDF)

pp. null

Maximizing CMP Throughput with Mediocre Cores (Abstract)

John D. Davis , Stanford University
James Laudon , Sun Microsystems, Inc.
Kunle Olukotun , Stanford University
pp. 51-62

Characterization of TCC on Chip-Multiprocessors (Abstract)

Brian D. Carlstrom , Computer Systems Laboratory, Stanford University
Christos Kozyrakis , Computer Systems Laboratory, Stanford University
Hassan Chafi , Computer Systems Laboratory, Stanford University
Lance Hammond , Computer Systems Laboratory, Stanford University
Kunle Olukotun , Computer Systems Laboratory, Stanford University
Austen McDonald , Computer Systems Laboratory, Stanford University
Chi Cao Minh , Computer Systems Laboratory, Stanford University
JaeWoong Chung , Computer Systems Laboratory, Stanford University
pp. 63-74

Store-Ordered Streaming of Shared Memory (Abstract)

Chris Gniady , Computer Science Dept. University of Arizona
Jangwoo Kim , Computer Architecture Laboratory (CALCM)
Anastassia Ailamaki , Computer Architecture Laboratory (CALCM) Carnegie Mellon University
Stephen Somogyi , Computer Architecture Laboratory (CALCM)
Babak Falsafi , Computer Architecture Laboratory (CALCM) Carnegie Mellon University
Thomas F. Wenisch , Computer Architecture Laboratory (CALCM)
Nikolaos Hardavellas , Computer Architecture Laboratory (CALCM)
pp. 75-86
DYNAMIC OPTIMIZATION (TRACK I)

null (PDF)

pp. null

An Event-Driven Multithreaded Dynamic Optimization Framework (Abstract)

Brad Calder , Department of Computer Science and Engineering University of California, San Diego
Dean M. Tullsen , Department of Computer Science and Engineering University of California, San Diego
Weifeng Zhang , Department of Computer Science and Engineering University of California, San Diego
pp. 87-98

Design and Implementation of a Compiler Framework for Helper Threading on Multi-core Processors (Abstract)

Partha Tirumalai , Scalable Systems Group Sun Microsystems, Inc.
Yonghong Song , Scalable Systems Group Sun Microsystems, Inc.
Spiros Kalogeropulos , Scalable Systems Group Sun Microsystems, Inc.
pp. 99-109

Compiler Directed Early Register Release (Abstract)

Michael F.P. O?Boyle , Member of HiPEAC, School of Informatics, University of Edinburgh
Antonio Gonzalez , Intel Labs Universitat Polit`ecnica de Catalunya
O?guz Ergin , Dept. Computer Architecture,
Jaume Abella , Intel Labs Universitat Polit`ecnica de Catalunya
Timothy M. Jones , Member of HiPEAC, School of Informatics, University of Edinburgh
pp. 110-122
COMPILER ANALYSIS A (TRACK II)

null (PDF)

pp. null

Automatic Selection of Compiler Options Using Non-parametric Inferential Statistics (Abstract)

P.M.W. Knijnenburg , LIACS, Leiden University The Netherlands
M. Haneda , LIACS, Leiden University The Netherlands
H.A.G. Wijshoff , LIACS, Leiden University The Netherlands
pp. 123-132

Data Centric Transformations on Non-Integer Iteration Spaces (Abstract)

Swarup Kumar Sahoo , Department of Computer Science and Engineering Ohio State University, Columbus OH
Gagan Agrawal , Department of Computer Science and Engineering Ohio State University, Columbus OH
pp. 133-142

Efficient Techniques for Advanced Data Dependence Analysis (Abstract)

Konstantinos Kyriakopoulos , Department of Computer Science The University of Texas at San Antonio
Kleanthis Psarris , Department of Computer Science The University of Texas at San Antonio
pp. 143-156
Keynote Address
COMPILING FOR NOVEL ARCHITECTURES

null (PDF)

pp. null

Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor (Abstract)

Jeremy Buhler , Department of Computer Science and Engineering Washington University in St.Louis
Patrick Crowley , Department of Computer Science and Engineering Washington University in St.Louis
Ben Wun , Department of Computer Science and Engineering Washington University in St.Louis
pp. 173-184

Automatic Tuning Matrix Multiplication Performance on Graphics Hardware (Abstract)

Marc Snir , University of Illinois Urbana Champaign
Changhao Jiang , University of Illinois Urbana Champaign
pp. 185-196
VLIW AND PERFORMANCE ANALYSIS

null (PDF)

pp. null

A Distributed Control Path Architecture for VLIW Processors (Abstract)

Michael Schlansker , Hewlett Packard Laboratories
Kevin Fan , Advanced Computer Architecture Laboratory University of Michigan - Ann Arbor, MI
Hongtao Zhong , Advanced Computer Architecture Laboratory University of Michigan - Ann Arbor, MI
Scott Mahlke , Advanced Computer Architecture Laboratoryv University of Michigan - Ann Arbor, MI
Scott Mahlke , Advanced Computer Architecture Laboratoryv University of Michigan - Ann Arbor, MI
pp. 197-206

Variable-Based Multi-module Data Caches for Clustered VLIW Processors (Abstract)

Antonio Gonz?lez , Intel Barcelona Research Center Intel Labs, Universitat Polit?cnica de Catalunya
Xavier Vera , Intel Barcelona Research Center Intel Labs, Universitat Polit?cnica de Catalunya
Jes? S?nchez , Intel Barcelona Research Center Intel Labs, Universitat Polit?cnica de Catalunya
Enric Gibert , Departament d?Arquitectura de Computadors Universitat Polit?cnica de Catalunya, Barcelona
Jaume Abella , Departament d?Arquitectura de Computadors Universitat Polit?cnica de Catalunya, Barcelona
pp. 207-217

Performance Analysis of System Overheads in TCP/IP Workloads (Abstract)

Steven K. Reinhardt , Advanced Computer Architecuture Lab EECS Department, University of Michigan
Ronald G. Dreslinski , Advanced Computer Architecuture Lab EECS Department, University of Michigan
Andrew L. Schultz , Advanced Computer Architecuture Lab EECS Department, University of Michigan
Nathan L. Binkert , Advanced Computer Architecuture Lab EECS Department, University of Michigan
Lisa R. Hsu , Advanced Computer Architecuture Lab EECS Department, University of Michigan
Ali G. Saidi , Advanced Computer Architecuture Lab EECS Department, University of Michigan
pp. 218-230
MICROARCHITECTURE (TRACK I)

null (PDF)

pp. null

Dual-Core Execution: Building a Highly Scalable Single-Thread Instruction Window (Abstract)

Huiyang Zhou , School of Computer Science, University of Central Florida
pp. 231-242

A Simple Divide-and-Conquer Approach for Neural-Class Branch Prediction (Abstract)

Gabriel H. Loh , College of Computing Georgia Institute of Technology Atlanta, GA, USA
pp. 243-254

Trace Cache Sampling Filter (Abstract)

Avi Mendelson , Intel Corporation Haifa, Israel
Avinoam Kolodny , Department of Electrical Engineering Technion, Haifa, Israel
Michael Behar , Department of Electrical Engineering
pp. 255-266
COMPILER ANALYSIS B (TRACK II)

null (PDF)

pp. null

Communication Optimizations for Fine-Grained UPC Applications (Abstract)

Costin Iancu , Lawrence Berkeley National Laboratory
Wei-Yu Chen , University of California at Berkeley Lawrence Berkeley National Laboratory
Katherine Yelick , University of California at Berkeley Lawrence Berkeley National Laboratory
pp. 267-278

HUNTing the Overlap (Abstract)

Parry Husbands , Computational Research Division, Lawrence Berkeley National Laboratory
Paul Hargrove , Computational Research Division, Lawrence Berkeley National Laboratory
Costin Iancu , Computational Research Division, Lawrence Berkeley National Laboratory
pp. 279-290

Deep Jam: Conversion of Coarse-Grain Parallelism to Instruction-Level and Vector Parallelism for Irregular Applications (Abstract)

Albert Cohen , ALCHEMY Group, INRIA Futurs and LRI, Universit? Paris-Sud, France
William Jalby , LRC ITACA, CEA/DAM and Universit? de Versailles Saint-Quentin, France
Patrick Carribault , Bull SA, Les Clayes sous Bois, France
pp. 291-302
RELIABILITY AND FAULT TOLERANCE

null (PDF)

pp. null

Memory State Compressors for Giga-Scale Checkpoint/Restore (Abstract)

Alexandros Kostopoulos , Department of Informatics and Telecommunications University of Athens
Andreas Moshovos , Electrical and Computer Engineering University of Toronto
pp. 303-314

Exploiting Coarse-Grain Verification Parallelism for Power-Efficient Fault Tolerance (Abstract)

Michael C. Huang , Department of Electrical & Computer Engineering University of Rochester
Edwin J. Tan , Department of Electrical & Computer Engineering University of Rochester
M. Wasiur Rashid , Department of Electrical & Computer Engineering University of Rochester
David H. Albonesi , Computer Systems Laboratory Cornell University
pp. 315-328
MEMORY

null (PDF)

pp. null

Memory Coloring: A Compiler Approach for Scratchpad Memory Management (Abstract)

Lin Gao , Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales
Jingling Xue , National ICT Australia
Lian Li , Programming Languages and Compilers Group School of Computer Science and Engineering University of New South Wales
pp. 329-338

Multiple Page Size Modeling and Optimization (Abstract)

Evelyn Duesterwald , IBM T.J. Watson Research Center
Peter F. Sweeney , IBM T.J. Watson Research Center
Robert W. Wisniewski , IBM T.J. Watson Research Center
Calin Cascaval , IBM T.J. Watson Research Center
pp. 339-349

Future Execution: A Hardware Prefetching Technique for Chip Multiprocessors (Abstract)

Ilya Ganusov , Computer Systems Laboratory Cornell University
Martin Burtscher , Computer Systems Laboratory Cornell University
pp. 350-360
Author Index

Author Index (PDF)

pp. 361
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