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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2005)
St. Louis, Missouri
Sept. 17, 2005 to Sept. 21, 2005
ISSN: 1089-795X
ISBN: 0-7695-2429-X
pp: 207-217
Enric Gibert , Departament d?Arquitectura de Computadors Universitat Polit?cnica de Catalunya, Barcelona
Jaume Abella , Departament d?Arquitectura de Computadors Universitat Polit?cnica de Catalunya, Barcelona
Jes? S?nchez , Intel Barcelona Research Center Intel Labs, Universitat Polit?cnica de Catalunya
Xavier Vera , Intel Barcelona Research Center Intel Labs, Universitat Polit?cnica de Catalunya
Antonio Gonz?lez , Intel Barcelona Research Center Intel Labs, Universitat Polit?cnica de Catalunya
ABSTRACT
<p>Memory structures consume an important fraction of the total processor energy. One solution to reduce the energy consumed by cache memories consists of reducing their supply voltage and/or increase their threshold voltage at an expense in access time. We propose to divide the L1 data cache into two cache modules for a clustered VLIW processor consisting of two clusters. Such division is done on a variable basis so that the address of a datum determines its location. Each cache module is assigned to a cluster and can be set up as a fast power-hungry module or as a slow power-aware module. We also present compiler techniques in order to distribute variables between the two cache modules and generate code accordingly. We have explored several cache configurations using the Mediabench suite and we have observed that the best distributed cache organization outperforms traditional cache organizations by 19%-31% in energy-delay2 and by 11%-29% in energy?delay. In addition, we also explore a reconfigurable distributed cache, where the cache can be reconfigured on a context switch. This reconfigurable scheme further outperforms the best previous distributed organization by 3%-4%.</p>
INDEX TERMS
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CITATION
Enric Gibert, Jaume Abella, Jes? S?nchez, Xavier Vera, Antonio Gonz?lez, "Variable-Based Multi-module Data Caches for Clustered VLIW Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 207-217, 2005, doi:10.1109/PACT.2005.40
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