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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2005)
St. Louis, Missouri
Sept. 17, 2005 to Sept. 21, 2005
ISSN: 1089-795X
ISBN: 0-7695-2429-X
pp: 173-184
Ben Wun , Department of Computer Science and Engineering Washington University in St.Louis
Jeremy Buhler , Department of Computer Science and Engineering Washington University in St.Louis
Patrick Crowley , Department of Computer Science and Engineering Washington University in St.Louis
ABSTRACT
<p>While general-purpose processors have only recently employed chip multiprocessor (CMP) architectures, network processors (NPs) have used heterogeneous multi-core architectures since the late 1990s. NPs differ qualitatively from workstation and server CMPs in that they replicate many simple, highly efficient processor cores on a chip, rather than a small number of sophisticated superscalar CPUs. In this paper, we compare the performance of one such NP, the Intel IXP 2850, to that of the Intel Pentium 4 when executing a scientific computing workload with a high degree of thread-level parallelism. Our target program, HMMer, is a bioinformatics tool that identifies conserved motifs in protein sequences. HMMer represents motifs as hidden Markov models (HMMs) and spends most of its time executing the well-known Viterbi algorithm to align proteins to these models. Our observations of HMMer on the IXP are therefore relevant to computations in many other domains that rely on the Viterbi algorithm. We show that the IXP achieves a speedup of 1.82 over the Pentium, despite the Pentium?s 1.85x faster clock. Moreover, we argue that nextgeneration IXP NPs will likely provide a 10-20x speedup for our workload over the IXP 2850, in contrast to 5-10x speedup expected from a next-generation Pentium-based CMP.</p>
INDEX TERMS
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CITATION
Ben Wun, Jeremy Buhler, Patrick Crowley, "Exploiting Coarse-Grained Parallelism to Accelerate Protein Motif Finding with a Network Processor", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 173-184, 2005, doi:10.1109/PACT.2005.21
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