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Proceedings. 13th International Conference on Parallel Architecture and Compilation Techniques, 2004. PACT 2004. (2004)
Antibes Juan-les-Pins, France
Sept. 29, 2004 to Oct. 3, 2004
ISSN: 1089-795X
ISBN: 0-7695-2229-7
TABLE OF CONTENTS

Code generation in the polyhedral model is easier than you think (PDF)

C. Bastoul , Lab. PRiSM, Univ. de Versailles Saint Quentin, France
pp. 7-16

A compiler framework for recovery code generation in general speculative optimizations (PDF)

J. Lin , Dept. of Comput. Sci., Minnesota Univ., MN, USA
W.-C. Hsu , Dept. of Comput. Sci., Minnesota Univ., MN, USA
P.-C. Yew , Dept. of Comput. Sci., Minnesota Univ., MN, USA
pp. 17-28

A multi-platform co-array Fortran compiler (PDF)

Y. Dotsenko , Dept. of Comput. Sci., Rice Univ., Houston, TX, USA
C. Coarfa , Dept. of Comput. Sci., Rice Univ., Houston, TX, USA
J. Mellor-Crummey , Dept. of Comput. Sci., Rice Univ., Houston, TX, USA
pp. 29-40

Adding limited reconfigurability to superscalar processors (PDF)

M. Epalza , Signal Process. Inst., Swiss Fed. Inst. of Technol., Lausanne, Switzerland
pp. 53-62

Architectural support for enhanced SMT job scheduling (PDF)

A. Settle , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
J. Kihm , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
A. Janiszewski , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
D. Connors , Dept. of Electr. & Comput. Eng., Colorado Univ., Boulder, CO, USA
pp. 63-73

Static placement, dynamic issue (SPDI) scheduling for EDGE architectures (PDF)

Ramadass Nagarajan , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
S.K. Kushwaha , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
D. Burger , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
K.S. McKinley , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
C. Lin , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
S.W. Keckler , Dept. of Comput. Sci., Texas Univ., Austin, TX, USA
pp. 74-84

Impact of Java memory model on out-of-order multiprocessors (PDF)

T. Mitra , Sch. of Comput., Nat. Univ. of Singapore, Singapore
Abhik Roychoudhury , Sch. of Comput., Nat. Univ. of Singapore, Singapore
Q. Shen , Sch. of Comput., Nat. Univ. of Singapore, Singapore
pp. 99-110

Fair cache sharing and partitioning in a chip multiprocessor architecture (PDF)

S. Kim , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
D. Chandra , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Y. Solihin , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
pp. 111-122

Architectural support for high speed protection of memory integrity and confidentiality in multiprocessor systems (PDF)

W. Shi , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
H.-H.S. Lee , Coll. of Comput., Georgia Inst. of Technol., Atlanta, GA, USA
pp. 123-134

AC/DC: an adaptive data cache prefetcher (PDF)

K.J. Nesbit , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
A.S. Dhodapkar , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
J.E. Smith , Dept. of Electr. & Comput. Eng., Wisconsin Univ., Madison, WI, USA
pp. 135-145

The energy impact of aggressive loop fusion (PDF)

Y. Zhu , Dept. of Electr. & Comput. Eng., Rochester Univ., NY, USA
pp. 153-164

Scalable high performance cross-module inlining (PDF)

D.R. Chakrabarti , Java, Compilers, & Tools Lab., Hewlett-Packard Co., Cupertino, CA, USA
L.A. Lozano , Java, Compilers, & Tools Lab., Hewlett-Packard Co., Cupertino, CA, USA
X.D. Li , Java, Compilers, & Tools Lab., Hewlett-Packard Co., Cupertino, CA, USA
R. Hundt , Java, Compilers, & Tools Lab., Hewlett-Packard Co., Cupertino, CA, USA
S.-M. Liu , Java, Compilers, & Tools Lab., Hewlett-Packard Co., Cupertino, CA, USA
pp. 165-176

Decoupled software pipelining with the synchronization array (PDF)

R. Rangan , Dept. of Comput. Sci., Princeton Univ., NJ, USA
N. Vachharajani , Dept. of Comput. Sci., Princeton Univ., NJ, USA
M. Vachharajani , Dept. of Comput. Sci., Princeton Univ., NJ, USA
D.I. August , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 177-188

Fast paths in concurrent programs (PDF)

W. Xu , Dept. of Comput. Sci., Princeton Univ., NJ, USA
pp. 189-200

Compiler estimation of load imbalance overhead in speculative parallelization (PDF)

J. Dou , Sch. of Informatics, Edinburgh Univ., UK
M. Cintra , Sch. of Informatics, Edinburgh Univ., UK
pp. 203-214

Implementing malleability on MPI jobs (PDF)

G. Utrera , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
J. Corbalan , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
J. Labarta , Dept. d'Arquitectura de Computadors, Univ. Politecnica de Catalunya, Barcelona, Spain
pp. 215-224

The value evolution graph and its use in memory reference analysis (PDF)

S. Rus , Texas A&M Univ., TX, USA
D. Zhang , Texas A&M Univ., TX, USA
L. Rauchwerger , Texas A&M Univ., TX, USA
pp. 243-254

TO-Lock: removing lock overhead using the owners' temporal locality (PDF)

T. Ogasawara , Tokyo Res. Lab., IBM Japan Ltd., Tokyo, Japan
H. Komatsu , Tokyo Res. Lab., IBM Japan Ltd., Tokyo, Japan
T. Nakatani , Tokyo Res. Lab., IBM Japan Ltd., Tokyo, Japan
pp. 255-266

An adaptive algorithm selection framework (PDF)

H. Yu , IBM Thomas J. Watson Res. Center, Yorktown Heights, NY, USA
pp. 278-289
Session 4: Compiler Optimizations

Scalable High Performance Cross-Module Inlining (Abstract)

Dhruva R. Chakrabarti , Hewlett-Packard Company, Cupertino, CA
Luis A. Lozano , Hewlett-Packard Company, Cupertino, CA
Xinliang D. Li , Hewlett-Packard Company, Cupertino, CA
Robert Hundt , Hewlett-Packard Company, Cupertino, CA
Shin-Ming Liu , Hewlett-Packard Company, Cupertino, CA
pp. 165-176

Decoupled Software Pipelining with the Synchronization Array (Abstract)

Ram Rangan , Princeton University
Neil Vachharajani , Princeton University
Manish Vachharajani , Princeton University
David I. August , Princeton University
pp. 177-188

Fast Paths in Concurrent Programs (Abstract)

Wen Xu , Princeton University
Sanjeev Kumar , Intel Corporation
Kai Li , Princeton University
pp. 189-200
Session 5: Parallel Systems

Compiler Estimation of Load Imbalance Overhead in Speculative Parallelization (Abstract)

Jialin Dou , University of Edinburgh, UK
Marcelo Cintra , University of Edinburgh, UK
pp. 203-214

Implementing Malleability on MPI Jobs (Abstract)

Gladys Utrera , Universitat Polit?cnica de Catalunya (UPC)
Julita Corbal? , Universitat Polit?cnica de Catalunya (UPC)
Jes? Labarta , Universitat Polit?cnica de Catalunya (UPC)
pp. 215-224

Partitioning of Code for a Massively Parallel Machine (Abstract)

Michael Ball , Sun Microsystems, Menlo Park, CA
Cristina Cifuentes , Sun Microsystems Labs, Mountain View, CA
Deepankar Bairagi , Sun Microsystems, Menlo Park, CA
pp. 225-236
Keynote Address
Session 6: Memory Parallelism

The Value Evolution Graph and its Use in Memory Reference Analysis (Abstract)

Silvius Rus , Texas A&M University
Dongmin Zhang , Texas A&M University
Lawrence Rauchwerger , Texas A&M University
pp. 243-254

TO-Lock: Removing Lock Overhead Using the Owners' Temporal Locality (Abstract)

Takeshi Ogasawara , Tokyo Research Laboratory, IBM Japan
Hideaki Komatsu , Tokyo Research Laboratory, IBM Japan
Toshio Nakatani , Tokyo Research Laboratory, IBM Japan
pp. 255-266

The Stream Virtual Machine (Abstract)

Francois Labonte , Stanford University
Peter Mattson , Reservoir Labs
Ian Buck , Stanford University
Christos Kozyrakis , Stanford University
Mark Horowitz , Stanford University
pp. 267-277

An Adaptive Algorithm Selection Framework (Abstract)

Hao Yu , IBM T. J. Watson Research Ctr, Yorktown Heights, NY
Dongmin Zhang , Texas A&M University
Lawrence Rauchwerger , Texas A&M University
pp. 278-289

Author Index (PDF)

pp. 291
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