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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2003)
New Orleans, Louisiana
Sept. 27, 2003 to Oct. 1, 2003
ISSN: 1089-795X
ISBN: 0-7695-2021-9
TABLE OF CONTENTS
Introduction

Reviewers (PDF)

pp. xii
Keynote 1
Session 1: Multithreading

Constraint Graph Analysis of Multithreaded Programs (Abstract)

Harold W. Cain , University of Wisconsin-Madison
Ravi Nair , IBM T.J. Watson Research Center
Mikko H. Lipasti , University of Wisconsin-Madison
pp. 4

The Impact of Resource Partitioning on SMT Processors (Abstract)

Steven K. Reinhardt , University of Michigan
Steven E. Raasch , University of Michigan
pp. 15

Initial Observations of the Simultaneous Multithreading Pentium 4 Processor (Abstract)

Dean M. Tullsen , University of California at San Diego
Nathan Tuck , University of California at San Diego
pp. 26
Session 2: Instruction-Level Parallelism

Efficient Resource Management during Instruction Scheduling for the EPIC Architecture (Abstract)

Dong-Yuan Chen , Intel Corporation
Chen Fu , Chinese Academy of Sciences
Roy Ju , Intel Corporation
Lixia Liu , Intel Corporation
Shuxin Yang , Chinese Academy of Sciences
Chengyong Wu , Chinese Academy of Sciences
pp. 36

Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency (Abstract)

Aneesh Aggarwal , University of Maryland at College Park
Manoj Franklin , University of Maryland at College Park
pp. 46

Y-Branches: When You Come to a Fork in the Road, Take It (Abstract)

Michael Fertig , University of Illinois at Urbana-Champaign
Nicholas Wang , University of Illinois at Urbana-Champaign
Sanjay Patel , University of Illinois at Urbana-Champaign
pp. 56
Session 3: Cache Optimizations

Optimizing Program Locality Through CMEs and GAs (Abstract)

Xavier Vera , Mälardalens Högskola
Josep Llosa , Universitat Politècnica de Catalunya-Barcelona
Jaume Abella , Universitat Politècnica de Catalunya-Barcelona
Antonio González , Universitat Politècnica de Catalunya-Barcelona
pp. 68

Miss Rate Prediction across All Program Inputs (Abstract)

Yutao Zhong , University of Rochester
Chen Ding , University of Rochester
Steven G. Dropsho , University of Rochester
pp. 79

Compiler-Directed Content-Aware Prefetching for Dynamic Data Structures (Abstract)

Hassan Al-Sukhni , University of Colorado at Boulder
Daniel A. Connors , University of Colorado at Boulder
Ian Bratt , University of Colorado at Boulder
pp. 91
Keynote 2
Session 4: Compiler Techniques and Domain-Specific Optimizations

Inter-Procedural Loop Fusion, Array Contraction and Rotation (Abstract)

Wei Li , Intel Compiler Laboratory
John Ng , Intel Compiler Laboratory
Robert Cox , Intel Compiler Laboratory
Dattatraya Kulkarni , Intel Compiler Laboratory
Scott Bobholz , Intel Compiler Laboratory
pp. 114

Spill Code Minimization by Spill Code Motion (Abstract)

Akira Koseki , IBM Tokyo Research Laboratory
Hideaki Komatsu , IBM Tokyo Research Laboratory
Toshio Nakatani , IBM Tokyo Research Laboratory
pp. 125
Session 5: Logging, Tracing, Profiling

An Efficient Online Path Profiling Framework for Java Just-In-Time Compilers (Abstract)

Toshio Suganuma , IBM Tokyo Research Laboratory
Toshiaki Yasue , IBM Tokyo Research Laboratory
Hideaki Komatsu , IBM Tokyo Research Laboratory
Toshio Nakatani , IBM Tokyo Research Laboratory
pp. 148

Compressing Extended Program Traces Using Value Predictors (Abstract)

Metha Jeeradit , Cornell University
Martin Burtscher , Cornell University
pp. 159

Using Software Logging to Support Multi-Version Buffering in Thread-Level Speculation (Abstract)

José María Llabería , Universitat Politècnica de Catalunya
Lawrence Rauchwerger , Texas A&M University
Víctor Viñals , Universidad de Zaragoza
Josep Torrellas , University of Illinois at Urbana-Champaign
Milos Prvulovic , University of Illinois at Urbana-Champaign
María Jesús Garzarán , University of Illinois at Urbana-Champaign
pp. 170
Session 6: Multiprocessors

Reactive Multi-Word Synchronization for Multiprocessors (Abstract)

Phuong Hoai Ha , Chalmers University of Technology
Philippas Tsigas , Chalmers University of Technology
pp. 184

Design Trade-Offs in High-Throughput Coherence Controllers (Abstract)

Josep Torrellas , University of Illinois at Urbana-Champaign
Anthony-Trung Nguyen , Intel Corporation
pp. 194

Memory Hierarchy Design for a Multiprocessor Look-up Engine (Abstract)

Neal Sidhwaney , University of Washington
Douglas Low , University of Washington
Jean-Loup Baer , University of Washington
Patrick Crowley , University of Washington
pp. 206
Keynote 3
Session 7: Application Characterization

Characterizing and Predicting Program Behavior and its Variability (Abstract)

Sandhya Dwarkadas , University of Rochester
Călin Caşcaval , IBM T.J. Watson Research
Evelyn Duesterwald , IBM T.J. Watson Research
pp. 220

Redeeming IPC as a Performance Metric for Multithreaded Programs (Abstract)

Harold W. Cain , University of Wisconsin-Madison
Kevin M. Lepak , University of Wisconsin-Madison
Mikko H. Lipasti , University of Wisconsin-Madison
pp. 232

Picking Statistically Valid and Early Simulation Points (Abstract)

Brad Calder , University of California at San Diego
Greg Hamerly , University of California at San Diego
Erez Perelman , University of California at San Diego
pp. 244
Session 8: Register Design Issues

Reducing Datapath Energy through the Isolation of Short-Lived Operands (Abstract)

Oguz Ergin , State University of New York at Binghamton
Dmitry Ponomarev , State University of New York at Binghamton
Gurhan Kucuk , State University of New York at Binghamton
Kanad Ghose , State University of New York at Binghamton
pp. 258

Resolving Register Bank Conflicts for a Network Processor (Abstract)

Santosh Pande , Georgia Institute of Technology
Xiaotong Zhuang , Georgia Institute of Technology
pp. 269
Author Index

Author Index (PDF)

pp. 279
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