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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2003)
New Orleans, Louisiana
Sept. 27, 2003 to Oct. 1, 2003
ISSN: 1089-795X
ISBN: 0-7695-2021-9
pp: 206
Jean-Loup Baer , University of Washington
Douglas Low , University of Washington
Patrick Crowley , University of Washington
Neal Sidhwaney , University of Washington
ABSTRACT
<p>We investigate the implementation of IP look-up for core routers using multiple microengines and a tailored memory hierarchy. The main architectural concerns are limiting the number of and contention for memory accesses.</p> <p>Using a level compressed trie as an index, we show the impact of the main parameter, the root branching factor, on the memory capacity and number of memory accesses. Despite the lack of locality, we show how a cache can reduce the required memory capacity and limit the amount of expensive multibanking. Results of simulation experiments using contemporary routing tables show that the architecture scales well, at least up to 16 processors, and that the presence of a small on-chip cache increases throughput significantly, up to 65% over an architecture with the same number of processors but without a cache, all while reducing the amount of required off-chip memory.</p>
INDEX TERMS
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CITATION
Jean-Loup Baer, Douglas Low, Patrick Crowley, Neal Sidhwaney, "Memory Hierarchy Design for a Multiprocessor Look-up Engine", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 206, 2003, doi:10.1109/PACT.2003.1238016
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