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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2003)
New Orleans, Louisiana
Sept. 27, 2003 to Oct. 1, 2003
ISSN: 1089-795X
ISBN: 0-7695-2021-9
pp: 135
Mauricio Breternitz, Jr. , Intel Corporation
Herbert Hum , Intel Corporation
Sanjeev Kumar , Intel Corporation
ABSTRACT
<p>Graphics and media processing is quickly emerging to become one of the key computing workloads. Programmable graphics processors give designers extra flexibility by running a small program for each fragment in the graphics pipeline. This paper investigates low-cost mechanisms to obtain good performance for modern graphics programs on a general purpose CPU.</p> <p>This paper presents a compiler that compiles SIMD graphics program and generates efficient code on a general purpose CPU. The generated code can process between 25-0.3 million vertices per second on a 2.2 GHz Intel Pentium® 4 processor for a group of typical graphics programs.</p> <p>This paper also evaluates the impact of three changes in the architecture and compiler. Adding support for new specialized instructions improves the performance of the programs by 27.4 %. on average. A novel compiler optimization called mask analysis improves the performance of the programs by 19.5 % on average. Increasing the number of architectural SIMD registers from 8 to 16 registers significantly reduces the number of memory accesses due to register spills.</p>
INDEX TERMS
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CITATION
Mauricio Breternitz, Jr., Herbert Hum, Sanjeev Kumar, "Compilation, Architectural Support, and Evaluation of SIMD Graphics Pipeline Programs on a General-Purpose CPU", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 135, 2003, doi:10.1109/PACT.2003.1238010
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