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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2003)
New Orleans, Louisiana
Sept. 27, 2003 to Oct. 1, 2003
ISSN: 1089-795X
ISBN: 0-7695-2021-9
pp: 79
Yutao Zhong , University of Rochester
Chen Ding , University of Rochester
Steven G. Dropsho , University of Rochester
ABSTRACT
Improving cache performance requires understanding cache behavior. However, measuring cache performance for one or two data input sets provides little insight into how cache behavior varies across all data input sets. This paper uses our recently published locality analysis to generate a parameterized model of program cache behavior. Given a cache size and associativity, this model predicts the miss rate for arbitrary data input set sizes. This model also identifies critical data input sizes where cache behavior exhibits marked changes. Experiments show this technique is within 2% of the hit rate for set associative caches on a set of integer and floating-point programs.
INDEX TERMS
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CITATION
Yutao Zhong, Chen Ding, Steven G. Dropsho, "Miss Rate Prediction across All Program Inputs", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 79, 2003, doi:10.1109/PACT.2003.1238004
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