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2003 12th International Conference on Parallel Architectures and Compilation Techniques (2003)
New Orleans, Louisiana
Sept. 27, 2003 to Oct. 1, 2003
ISSN: 1089-795X
ISBN: 0-7695-2021-9
pp: 46
Aneesh Aggarwal , University of Maryland at College Park
Manoj Franklin , University of Maryland at College Park
ABSTRACT
As feature sizes are becoming smaller, wire delays are becoming very critical. Clustering is a popular decentralization approach to reduce the impact of shrinking technologies on clock speed. In this approach, the centralized instruction window is replaced with multiple smaller windows, called clusters (PEs). The performance of these clustered processors depends on the amount of inter-PE communication and load imbalance incurred by the distribution algorithm used to distribute instructions among the PEs. In this paper, we investigate a novel approach of reducing the impact of inter-PE communication latency, while preserving good load balance. The basic idea is to selectively replicate instructions in those PEs where their results are required. The replication is done based on heuristics that weigh the potential benefits of replication. We found that with instruction replication, the IPC of a clustered processor is significantly higher than that obtained without instruction replication and is within just 8% of that of a super-scalar configuration with a centralized instruction window.
INDEX TERMS
Clustered processors, Instruction Replication, Load Imbalance, Inter-PE communication, Instruction Distribution, Instructions per Cycle
CITATION

A. Aggarwal and M. Franklin, "Instruction Replication: Reducing Delays Due to Inter-PE Communication Latency," 2003 12th International Conference on Parallel Architectures and Compilation Techniques(PACT), New Orleans, Louisiana, 2003, pp. 46.
doi:10.1109/PACT.2003.1238001
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