The Community for Technology Leaders
Proceedings.International Conference on Parallel Architectures and Compilation Techniques (2002)
Charlottesville, Virginia
Sept. 22, 2002 to Sept. 25, 2002
ISSN: 1089-795X
ISBN: 0-7695-1620-3

Reviewers (PDF)

pp. xvi
Keynote Address
Session 1: Data Parallelism and Threading

Increasing and Detecting Memory Address Congruence (Abstract)

Samuel Larsen , Massachusetts Institute of Technology
Emmett Witchel , Massachusetts Institute of Technology
Saman Amarasinghe , Massachusetts Institute of Technology
pp. 18

Transparent Threads: Resource Sharing in SMT Processors for High Single-Thread Performance (Abstract)

Gautham K. Dorai , University of Maryland at College Park
Donald Yeung , University of Maryland at College Park
pp. 30
Session 2: Compiler Support for Architecture

Compiler-Controlled Caching in Superword Register Files for Multimedia Extension Architectures (Abstract)

Jaewook Shin , University of Southern California
Jacqueline Chame , University of Southern California
Mary W. Hall , University of Southern California
pp. 45

Effective Compilation Support for Variable Instruction Set Architecture (Abstract)

Jack Liu , Cognigine Corporation
Timothy Kong , Cognigine Corporation
Fred Chow , Cognigine Corporation
pp. 56

A Framework for Parallelizing Load/Stores on Embedded Processors (Abstract)

Xiaotong Zhuang , Georgia Institute of Technology
Santosh Pande , Georgia Institute of Technology
John S. Greenland Jr. , Green Hills Software, Inc.
pp. 68
Session 3: Program Characterization

Workload Design: Selecting Representative Program-Input Pairs (Abstract)

Lieven Eeckhout , Ghent University
Hans Vandierendonck , Ghent University
Koen De Bosschere , Ghent University
pp. 83

Dataflow Frequency Analysis Based on Whole Program Paths (Abstract)

Bernhard Scholz , Vienna University of Technology
Eduard Mehofer , University of Vienna
pp. 95

Quantifying Instruction Criticality (Abstract)

Eric S. Tune , University of California at San Diego
Dean M. Tullsen , University of California at San Diego
Brad Calder , University of California at San Diego
pp. 104
Keynote Address
Session 4: Power

Application Transformations for Energy and Performance-Aware Device Management (Abstract)

Taliver Heath , Rutgers University
Eduardo Pinheiro , Rutgers University
Jerry Hom , Rutgers University
Ulrich Kremer , Rutgers University
Ricardo Bianchini , Rutgers University
pp. 121

Leakage Energy Management in Cache Hierarchies (Abstract)

L. Li , Pennsylvania State University
I. Kadayif , Pennsylvania State University
Y-F. Tsai , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
M. Kandemir , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
A. Sivasubramaniam , Pennsylvania State University
pp. 131

Integrating Adaptive On-Chip Storage Structures for Reduced Dynamic Power (Abstract)

Steve Dropsho , University of Rochester
Alper Buyuktosunoglu , University of Rochester
Rajeev Balasubramonian , University of Rochester
David H. Albonesi , University of Rochester
Sandhya Dwarkadas , University of Rochester
Greg Semeraro , University of Rochester
Grigorios Magklis , University of Rochester
Michael L. Scott , University of Rochester
pp. 141
Session 5: Prediction

The Use of Prediction for Accelerating Upgrade Misses in cc-NUMA Multiprocessors (Abstract)

Manuel E. Acacio , Universidad de Murcia
José González , Intel Barcelona Research Center
José M. García , Universidad de Murcia
José Duato , Universidad Politécnica de Valencia
pp. 155
Session 6: Memory Performance

Speculative Sequential Consistency with Little Custom Storage (Abstract)

Chris Gniady , Carnegie Mellon University
Babak Falsafi , Carnegie Mellon University
pp. 179

Cost-Effective Compiler Directed Memory Prefetching and Bypassing (Abstract)

Daniel Ortega , Universidad Politécnica de Cataluña
Eduard Ayguadé , Universidad Politécnica de Cataluña
Jean-Loup Baer , University of Washington
Mateo Valero , Universidad Politécnica de Cataluña
pp. 189

Using the Compiler to Improve Cache Replacement Decisions (Abstract)

Zhenlin Wang , University of Massachusetts at Amherst
Kathryn S. McKinley , University of Texas at Austin
Arnold L. Rosenberg , University of Massachusetts at Amherst
Charles C. Weems , University of Massachusetts at Amherst
pp. 199
Session 7: Memory Aliasing

Software Bubbles: Using Predication to Compensate for Aliasing in Software Pipelines (Abstract)

Benjamin Goldberg , New York University
Emily Crutcher , New York University
Chad Huneycutt , Georgia Institute of Technology
Krishna Palem , Georgia Institute of Technology
pp. 211

Speculative Alias Analysis for Executable Code (Abstract)

Manel Fernández , Universitat Politècnica de Catalunya
Roger Espasa , Universitat Politècnica de Catalunya
pp. 222
Keynote Address
Session 8: Java and IA-64

Eliminating Exception Constraints of Java Programs for IA-64 (Abstract)

Kazuaki Ishizaki , IBM Research, Tokyo Research Laboratory
Tatsushi Inagaki , IBM Research, Tokyo Research Laboratory
Hideaki Komatsu , IBM Research, Tokyo Research Laboratory
Toshio Nakatani , IBM Research, Tokyo Research Laboratory
pp. 259
Session 9: Clustered Microarchitectures

Optimizing Loop Performance for Clustered VLIW Architectures (Abstract)

Yi Qian , Michigan Technological University
Steve Carr , Michigan Technological University
Philip Sweany , Texas Instruments
pp. 271

Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning (Abstract)

Jesús Sánchez , UPC and Intel Barcelona Research Center
Antonio González , UPC and Intel Barcelona Research Center
David Kaeli , Northeastern University
pp. 281

Efficient Interconnects for Clustered Microarchitectures (Abstract)

Joan-Manuel Parcerisa , Universitat Polit?cnica de Catalunya
Julio Sahuquillo , Universitat Polit?cnica de Val?ncia
Antonio González , Universitat Polit?cnica de Catalunya and Intel Barcelona Research Center
José Duato , Universitat Polit?cnica de Val?ncia
pp. 291
SIGARCH Conference Guidelines
Author Index

Author Index (PDF)

pp. 305
85 ms
(Ver 3.3 (11022016))