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Proceedings.International Conference on Parallel Architectures and Compilation Techniques (2002)
Charlottesville, Virginia
Sept. 22, 2002 to Sept. 25, 2002
ISSN: 1089-795X
ISBN: 0-7695-1620-3
pp: 291
Joan-Manuel Parcerisa , Universitat Polit?cnica de Catalunya
Julio Sahuquillo , Universitat Polit?cnica de Val?ncia
Antonio González , Universitat Polit?cnica de Catalunya and Intel Barcelona Research Center
José Duato , Universitat Polit?cnica de Val?ncia
ABSTRACT
<p>Clustering is an effective microarchitectural technique for reducing the impact of wire delays, the complexity, and the power requirements of microprocessors. In this work, we investigate the design of on-chip interconnection networks for clustered microarchitectures. This new class of interconnects has different demands and characteristics than traditional multiprocessor networks. In a clustered microarchitecture, a low inter-cluster communication latency is essential for high performance.</p> <p>We propose point-to-point interconnects together with an effective latency-aware instruction steering scheme and show that they achieve much better performance than bus-based interconnects. The results show that the connectivity of the network together with latency-aware steering schemes are key for high performance. We also show that these interconnects can be built with simple hardware and achieve a performance close to that of an idealized contention-free model.</p>
INDEX TERMS
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CITATION

J. Parcerisa, J. Sahuquillo, A. González and J. Duato, "Efficient Interconnects for Clustered Microarchitectures," Proceedings.International Conference on Parallel Architectures and Compilation Techniques(PACT), Charlottesville, Virginia, 2002, pp. 291.
doi:10.1109/PACT.2002.1106028
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