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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2002)
Charlottesville, Virginia
Sept. 22, 2002 to Sept. 25, 2002
ISSN: 1089-795X
ISBN: 0-7695-1620-3
pp: 131
A. Sivasubramaniam , Pennsylvania State University
M. J. Irwin , Pennsylvania State University
N. Vijaykrishnan , Pennsylvania State University
M. Kandemir , Pennsylvania State University
L. Li , Pennsylvania State University
I. Kadayif , Pennsylvania State University
Y-F. Tsai , Pennsylvania State University
ABSTRACT
Energy management is important for a spectrum of systems ranging from high-performance architectures to low-end mobile and embedded devices. With the increasing number of transistors, smaller feature sizes, lower supply and threshold voltages, the focus on energy optimization is shifting from dynamic to leakage energy. Leakage energy is of particular concern in dense cache memories that form a major portion of the transistor budget. In this work, we present several architectural techniques that exploit the data duplication across the different levels of cache hierarchy. Specifically, we employ both state-preserving (data-retaining) and state-destroying leakage control mechanisms to L2 subblocks when their data also exist in L1. Using a set of media and array-dominated applications, we demonstrate the effectiveness of the proposed techniques through cycle-accurate simulation. We also compare our schemes with the previously proposed cache decay policy. This comparison indicates that one of our schemes generates competitive results with cache decay.
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CITATION
A. Sivasubramaniam, M. J. Irwin, N. Vijaykrishnan, M. Kandemir, L. Li, I. Kadayif, Y-F. Tsai, "Leakage Energy Management in Cache Hierarchies", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 131, 2002, doi:10.1109/PACT.2002.1106012
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