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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2001)
Barcelona, Spain
Sept. 8, 2001 to Sept. 12, 2001
ISBN: 0-7695-1363-8
Session 1: Simulation and Modeling

Basic Block Distribution Analysis to Find Periodic Behavior and Simulation Points in Applications (Abstract)

Erez Perelman , University of California, San Diego
Brad Calder , University of California, San Diego
Timothy Sherwood , University of California, San Diego
pp. 0003

Modeling Superscalar Processors via Statistical Simulation (Abstract)

Sébastien Nussbaum , University of Wisconsin - Madison
James E. Smith , University of Wisconsin - Madison
pp. 0015
Session 2: Efficient Caches

Filtering Techniques to Improve Trace-Cache Efficiency (Abstract)

Ronny Ronen , Intel Corporation
Avi Mendelson , Intel Corporation
Roni Rosner , Intel Corporation
pp. 0037

Reactive-Associative Caches (Abstract)

Brannon Batson , Compaq Computer Corporation
T. N. Vijaykumar , Purdue University
pp. 0049

Adaptive Mode Control: A Static-Power-Efficient Cache Design (Abstract)

Thomas M. Conte , North Carolina State University
Mark C. Toburen , North Carolina State University
Huiyang Zhou , North Carolina State University
Eric Rotenberg , North Carolina State University
pp. 0061
Session 3: Specialized Instruction Sets

Implementation and Evaluation of the Complex Streamed Instruction Set (Abstract)

Stamatis Vassiliadis , Delft University of Technology
Harry A.G. Wijshoff , Leiden University
Ben Juurlink , Delft University of Technology
Dmitri Tcheressiz , Leiden University
pp. 0073

On the Efficiency of Reductions in ?-SIMD Media Extensions (Abstract)

Mateo Valero , Universitat Polit?cnica de Catalunya
Jesus Corbal , Universitat Polit?cnica de Catalunya
Roger Espasa , Universitat Polit?cnica de Catalunya
pp. 0083
Session 4: Prediction and Recovery

Boolean Formula-Based Branch Prediction for Future Technologies (Abstract)

Heather L. Hanson , The University of Texas at Austin
Daniel A. Jiménez , The University of Texas at Austin
Calvin Lin , The University of Texas at Austin
pp. 0097

Using Dataflow Based Context for Accurate Value Prediction (Abstract)

Manoj Franklin , University of Maryland
Renju Thomas , University of Maryland
pp. 0107

Recovery Mechanism for Latency Misprediction (Abstract)

Àngel Olivé , Universitat Polit?cnica de Catalunya
Enric Morancho , Universitat Polit?cnica de Catalunya
José María Llabería , Universitat Polit?cnica de Catalunya
pp. 0118
Session 5: Memory Optimization

A Cost Framework for Evaluating Integrated Restructuring Optimizations (Abstract)

John B. Carter , University of Utah
Wilson C. Hsieh , University of Utah
Bharat Chandramouli , University of Utah
Sally A. McKee , University of Utah
pp. 0131

Compiling for the Impulse Memory Controller (Abstract)

Xianglong Huang , University of Massachusetts, Amherst
Zhenlin Wang , University of Massachusetts, Amherst
Kathryn S. McKinley , University of Massachusetts, Amherst
pp. 0141
Session 6: Program Optimization

Code Reordering and Speculation Support for Dynamic Optimization Systems (Abstract)

Wen-mei W. Hwu , University of Illinois
Matthew C. Merten , University of Illinois
Erik M. Nystrom , University of Illinois
Ronald D. Barnes , University of Illinois
pp. 0163

A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors (Abstract)

Jesús Sánchez , Universitat Polit?cnica de Catalunya
Josep M. Codina , Universitat Polit?cnica de Catalunya
Antonio González , Universitat Polit?cnica de Catalunya
pp. 0175

Cache-Friendly Implementations of Transitive Closure (Abstract)

Michael Penner , University of Southern California
Viktor K Prasanna , University of Southern California
pp. 0185
Session 7: Technology Implications

Exploring the Design Space of Future CMPs (Abstract)

Stephen W. Keckler , The University of Texas at Austin
Jaehyuk Huh , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
pp. 0199

Area and System Clock Effects on SMT/CMP Processors (Abstract)

Jean-Luc Gaudiot , University of Southern California
James Burns , Intel
pp. 0211
Session 8: Parallel Machines

Limits on Speculative Module-Level Parallelism in Imperative and Object-Oriented Programs on CMP Platforms (Abstract)

Fredrik Warg , Chalmers University of Technology
Per Stenström , Chalmers University of Technology
pp. 0221

Compiler and Runtime Analysis for Efficient Communication in Data Intensive Applications (Abstract)

Gagan Agrawal , University of Delaware
Joel Saltz , University of Maryland, College Park
Renato Ferreira , University of Maryland, College Park
pp. 0231

Architectural Support for Parallel Reductions in Scalable Shared-Memory Multiprocessors (Abstract)

Lawrence Rauchwerger , Texas A&M University
María Jesús Garzarán , Universidad de Zaragoza
Ye Zhangy , University of Illinois at Urbana-Champaign
Alin Jula , Texas A&M University
Hao Yu , Texas A&M University
Josep Torrellas , University of Illinois at Urbana-Champaign
Milos Prvulovic , University of Illinois at Urbana-Champaign
pp. 0243
Session 9: Data Prefetching

Optimizing Software Data Prefetches with Rotating Registers (Abstract)

Rakesh Krishnaiyer , Intel Corporation
Kalyan Muthukumar , Intel Technology India Pvt Ltd
Gautam Doshi , Intel Corporation
pp. 0257

Multi-Chain Prefetching: Effective Exploitation of Inter-Chain Memory Parallelism for Pointer-Chasing Codes (Abstract)

Dongkeun Kim , Univ. of Maryland, College Park
Seungryul Choi , Univ. of Maryland, College Park
Donald Yeung , Univ. of Maryland, College Park
Nicholas Kohout , Intel Corp.
pp. 0268

Data Flow Analysis for Software Prefetching Linked Data Structures in Java (Abstract)

Brendon Cahoon , University of Massachusetts
Kathryn S. McKinley , University of Massachusetts
pp. 0280

Author Index (PDF)

pp. 0305
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