The Community for Technology Leaders
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2001)
Barcelona, Spain
Sept. 8, 2001 to Sept. 12, 2001
ISBN: 0-7695-1363-8
pp: 0199
Jaehyuk Huh , The University of Texas at Austin
Doug Burger , The University of Texas at Austin
Stephen W. Keckler , The University of Texas at Austin
ABSTRACT
Abstract: In this paper, we study the space of chip multiprocessor (CMP) organizations. We compare the area and performance trade-offs for CMP implementations to determine how many processing cores future server CMPs should have, whether the cores should have in-order or out-of-order issue, and how big the per-processor on-chip caches should be. We find that, contrary to some conventional wisdom, out-of-order processing cores will maximize job throughput on future CMPs. As technology shrinks, limited off-chip bandwidth will begin to curtail the number of cores that can be effective on a single die. Current projections show that the transistor/signal pin ratio will increase by a factor of 45 between 180 and 35 nanometer technologies. That disparity will force increases in per-processor cache capacities as technology shrinks, from 128KB at 100nm, to 256KB at 70nm, and to 1MB at 50 and 35nm, reducing the number of cores that would otherwise be possible.
INDEX TERMS
CITATION
Jaehyuk Huh, Doug Burger, Stephen W. Keckler, "Exploring the Design Space of Future CMPs", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0199, 2001, doi:10.1109/PACT.2001.953300
80 ms
(Ver 3.3 (11022016))