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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2001)
Barcelona, Spain
Sept. 8, 2001 to Sept. 12, 2001
ISBN: 0-7695-1363-8
pp: 0185
Michael Penner , University of Southern California
Viktor K Prasanna , University of Southern California
ABSTRACT
Abstract: In this paper we show cache-friendly implementations of the Floyd-Warshall algorithm for the All-Pairs Shortest-Path problem. We first compare the best commercial compiler optimizations available with standard cache-friendly optimizations and a simple improvement involving a block layout, which reduces TLB misses. We show approximately 15% improvements using these optimizations. We also develop a general representation, the Unidirectional Space Time Representation, which can be used to generate cache-friendly implementations for a large class of algorithms. We show analytically and experimentally that this representation can be used to minimize level-1 and level-2 cache misses and TLB misses and therefore exhibits the best overall performance. Using this representation we show a 2x improvement in performance with respect to the compiler optimized implementation. Experiments were conducted on Pentium III, Alpha, and MIPS R12000 machines using problem sizes between 1024 and 2048 vertices. We used the Simplescalar simulator to demonstrate improved cache performance.
INDEX TERMS
CITATION
Michael Penner, Viktor K Prasanna, "Cache-Friendly Implementations of Transitive Closure", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0185, 2001, doi:10.1109/PACT.2001.953299
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