Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2001)
Sept. 8, 2001 to Sept. 12, 2001
Enric Morancho , Universitat Polit?cnica de Catalunya
José María Llabería , Universitat Polit?cnica de Catalunya
Àngel Olivé , Universitat Polit?cnica de Catalunya
Abstract: Signalling result availability from the functional units to the instruction scheduler can increase the cycle time and/or the effective latency of the instructions. The knowledge of all instruction latencies would allow the instruction scheduler to operate without the need of external signalling. However, the latency of some instructions is unknown; but, the scheduler can optimistically predict the latency of these instructions and issue speculatively their dependent instructions. Although prediction techniques have great performance potential, their gain can vanish due to misprediction handling. For instance, holding speculatively scheduled instructions in the issue queue reduces its capacity to look-ahead for independent instructions. This paper evaluates a recovery mechanism for latency mispredictions that retains the speculatively issued instructions in a structure apart from the issue queue: the recovery buffer. When data becomes available after a latency misprediction, the dependent instructions will be re-issued from the recovery buffer. Moreover, in order to simplify the re-issue logic of the recovery buffer, the instructions will be recorded in issue order. On mispredictions, the recovery buffer increases the effective capacity of the issue queue to hold instructions waiting for operands. Our evaluations in integer benchmarks show that the recovery-buffer mechanism reduces issue-queue size requirements about 20-25%. Also, this mechanism is less sensitive to the verification delay than the recovery mechanism that retains the instructions in the issue queue.
Enric Morancho, José María Llabería, Àngel Olivé, "Recovery Mechanism for Latency Misprediction", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0118, 2001, doi:10.1109/PACT.2001.953293