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Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622) (2000)
Philadelphia, Pennsylvania
Oct. 15, 2000 to Oct. 19, 2000
ISSN: 1089-795X
ISBN: 0-7695-0622-4

Introduction (PDF)

pp. viii

Reviewers (PDF)

pp. xi
Register Allocation and Analysis

Register Queues: A New Hardware/Software Approach to Efficient Software Pipelining (Abstract)

Mikhail Smelyanskiy , University of Michigan
Gary S. Tyson , University of Michigan
Edward S. Davidson , University of Michigan
pp. 3

Global Register Partitioning (Abstract)

Jason Hiser , University of Virginia
Steve Carr , Michigan Technological University
Philip Sweany , Michigan Technological University
pp. 13

Region Formation Analysis with Demand-Driven Inlining for Region-Based Optimization (Abstract)

Tom Way , University of Delaware
Ben Breech , University of Delaware
Lori Pollock , University of Delaware
pp. 24
Architectural Design

aSOC: A Scalable, Single-Chip Communications Architecture (Abstract)

Jian Liang , University of Massachusetts at Amherst
Sriram Swaminathan , University of Massachusetts at Amherst
Russell Tessier , University of Massachusetts at Amherst
pp. 37
Optimizations and Opportunities

A Lightweight Algorithm for Dynamic If-Conversion during Dynamic Optimization (Abstract)

Kim M. Hazelwood , North Carolina State University
Thomas M. Conte , North Carolina State University
pp. 71

Exploring the Limits of Sub-Word Level Parallelism (Abstract)

Kevin Scott , University of Virginia
Jack Davidson , University of Virginia
pp. 81

The Dynamic Trace Memorization Reuse Technique (Abstract)

Amarildo T. da Costa , Federal University of Rio de Janeiro
Felipe M. G. França , Federal University of Rio de Janeiro
Eliseu M.C. Filho , Federal University of Rio de Janeiro
pp. 92

Exploring Sub-Block Value Reuse for Superscalar Processors (Abstract)

Jian Huang , Sun Microsystems
David J. Lilja , University of Minnesota
pp. 100
High Performance Memory Techniques

Hiding Relaxed Memory Consistency with Compilers (Abstract)

Jaejin Lee , Michigan State University
David A. Padua , University of Illinois at Urbana-Champaign
pp. 111

Characterization of Silent Stores (Abstract)

Gordon B. Bell , University of Wisconsin
Kevin M. Lepak , University of Wisconsin
Mikko H. Lipasti , University of Wisconsin
pp. 133
Speculation and Prediction

On Some Implementation Issues for Value Prediction on Wide-Issue ILP Processors (Abstract)

Sang-Jeong Lee , Soonchunhyang University
Pen-Chung Yew , University of Minnesota
pp. 145

A Unified Compiler Framework for Control and Data Speculation (Abstract)

Roy Dz-ching Ju , Hewlett-Packard Company
Kevin Nomura , Hewlett-Packard Company
Uma Mahadevan , Hewlett-Packard Company
Le-Chun Wu , Hewlett-Packard Company
pp. 157

Applying Data Speculation in Modulo Scheduled Loops (Abstract)

Uma Mahadevan , Hewlett-Packard Company
Kevin Nomura , Hewlett-Packard Company
Roy Dz-ching Ju , Hewlett-Packard Company
Rick Hank , Hewlett-Packard Company
pp. 169
Branch Prediction

Branch Prediction in Multi-Threaded Processors (Abstract)

Jayanth Gummaraju , University of Maryland at College Park
Manoj Franklin , University of Maryland at College Park
pp. 179

The Effect of Code Reordering on Branch Prediction (Abstract)

Alex Ramirez , Universitat Politecnica de Catalunya
Josep L. Larriba-Pey , Universitat Politecnica de Catalunya
Mateo Valero , Universitat Politecnica de Catalunya
pp. 189

Dynamic Branch Prediction for a VLIW Processor (Abstract)

Jan Hoogerbrugge , Philips Research Laboratories
pp. 207
Parallel Computation

Fine Grained Multithreading with Process Calculi (Abstract)

Luís Lopes , University of Porto
Fernando Silva , University of Porto
Vasco T. Vasconcelos , University of Lisbon
pp. 217

Data Relation Vectors: A New Abstraction for Data Optimizations (Abstract)

Mahmut Kandemir , Pennsylvania State University
J. Ramanujam , Louisiana State University
pp. 227

Combined Selection of Tile Sizes and Unroll Factors Using Iterative Compilation (Abstract)

T. Kisuki , Leiden University
P.M.W. Knijnenburg , Leiden University
M.F.P. O'Boyle , Edinburgh University
pp. 237

Faster FFTs via Architecture-Cognizance (Abstract)

Kang Su Gatlin , University of California at San Diego
Larry Carter , University of California at San Diego
pp. 249

Hybrid Parallel Circuit Simulation Approaches (Abstract)

Edwin Naroska , University of Dortmund
Uwe Schwiegelshohn , University of Dortmund
Rung-Ji Shang , National Taiwan University
Feipei Lai , National Taiwan University
pp. 261

Multithreaded Programming of PC Clusters (Abstract)

Martin Schulz , Technische Universit?t M?nchen
pp. 271
Instruction Scheduling

A Fast Algorithm for Scheduling Instructions with Deadline Constraints on RISC Processors (Abstract)

Hui Wu , National University of Singapore
Joxan Jaffar , National University of Singapore
Roland Yap , National University of Singapore
pp. 281

Instruction Scheduling for Clustered VLIW DSPs (Abstract)

Rainer Leupers , University of Dortmund
pp. 291

Efficient Backtracking Instruction Schedulers (Abstract)

Santosh G. Abraham , Hewlett-Packard Laboratories
Waleed M. Meleis , Northeastern University
Ivan D. Baev , Northeastern University
pp. 301

Author Index (PDF)

pp. 309
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