Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622) (2000)
Oct. 15, 2000 to Oct. 19, 2000
Edwin Naroska , University of Dortmund
Uwe Schwiegelshohn , University of Dortmund
Rung-Ji Shang , National Taiwan University
Feipei Lai , National Taiwan University
In this paper, we address the parallel timing simulation of synchronous VLSI designs on networks of workstations (NOWs). Our approaches exploit the performance gap between cycles based simulators and timing simulator techniques and combine both methods to speedup timing simulation. Based on the technique we developed four different simulation methods, which are characterized by removing some communication between the timing simulators. In particular, we execute a timing simulator on each node of the NOW and use cycle-based simulation to produce synchronization information required by the timing simulators. One of our methods even does not need any communication at all and is hence well suited for parallel simulation on NOWs, which are typically characterized, by low bandwidth and high communication latency. Simulation results show that a significant speedup can be achieved even for very small circuits.
parallel timing simulation, workstation cluster, circuit simulation, cycle-based simulation
U. Schwiegelshohn, F. Lai, E. Naroska and R. Shang, "Hybrid Parallel Circuit Simulation Approaches," Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)(PACT), Philadelphia, Pennsylvania, 2000, pp. 261.