Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622) (2000)
Oct. 15, 2000 to Oct. 19, 2000
Alex Ramirez , Universitat Politecnica de Catalunya
Josep L. Larriba-Pey , Universitat Politecnica de Catalunya
Mateo Valero , Universitat Politecnica de Catalunya
Branch prediction accuracy is a very important factor for superscalar processor performance. The ability to predict the outcome of a branch allows the processor to effectively use a large instruction window, and extract a larger amount of Instruction Level Parallelism (ILP). In this paper, we will examine the effect of code layout optimizations on branch prediction accuracy and final processor performance. These code-reordering techniques align branches so that they tend to be not taken, achieving better instruction cache performance and increasing the fetch bandwidth. Here we focus on how these optimizations affect both static and dynamic branch prediction. Code reordering mainly increases the number of not taken branches, which benefits simple static predictors, which reach over 80% prediction accuracy with optimized codes. This branch direction change produces two effects on dynamic branch prediction: on the positive side, trades negative interference for neutral or positive interference in the prediction tables; on the negative side, it causes a worse distribution of the Branch History Register (BHR), causing many possible history values to be unused. Our results show that code reordering reduces negative Pattern History Table (PHT) interference, increasing branch prediction accuracy on small branch predictors. For example, a 0.5KB gshare improves from 91.4% to 93.6%, and a 0.4KB gskew predictor from 93.5% to 94.4%. For larger history lengths, the large amount of not taken branches can degrade predictor performance on dealiased schemes, like the 16KB agree predictor which goes from 96.2% to 95.8%. However, processor performance not only depends on branch prediction accuracy. Layout optimized codes have much better instruction cache performance, and wider fetch bandwidth. Our results show that when all three factors are considered together, code-reordering techniques always improve processor performance. For example, performance still increases by 8% with an agree predictor, which loses prediction accuracy, and it increases by 9% with a gshare predictor, which increases prediction accuracy.
M. Valero, J. L. Larriba-Pey and A. Ramirez, "The Effect of Code Reordering on Branch Prediction," Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)(PACT), Philadelphia, Pennsylvania, 2000, pp. 189.