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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (2000)
Philadelphia, Pennsylvania
Oct. 15, 2000 to Oct. 19, 2000
ISSN: 1089-795X
ISBN: 0-7695-0622-4
pp: 100
Jian Huang , Sun Microsystems
David J. Lilja , University of Minnesota
ABSTRACT
The performance potential of a value reuse mechanism depends on its reuse detection time, the number of reuses opportunities, and the amount of work saved by skipping each reuse unit. Since larger instruction groups typically have fewer reuse opportunities than smaller groups, but also provide greater benefit for each reuse-detection process, it is very important to find the balance point that provides the largest overall performance gain. We propose a new mechanism called sub-block reuse to balance the reuse granularity and the number of reuse opportunities. Our simulation results show that sub-block reuse with compiler assistance has a substantial and consistent potential to improve the performance of superscalar processors, with speedups ranging from 10% to 22%.
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CITATION
Jian Huang, David J. Lilja, "Exploring Sub-Block Value Reuse for Superscalar Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 100, 2000, doi:10.1109/PACT.2000.888335
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