Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622) (2000)
Oct. 15, 2000 to Oct. 19, 2000
Bruce R. Childers , University of Pittsburgh
Jack W. Davidson , University of Virginia
Application-specific instruction set processor (ASIP) design is a promising technique to meet the performance and cost goals of high-performance systems. ASIPs are especially valuable for embedded computing (e.g., digital cameras, color printers, cellular phones, etc.) where a small increase in performance and decrease in cost can have a large impact on a product's viability. Sutherland, Sproull, and Molnar have proposed a processor organization called the counterflow pipeline (CFP) that is appropriate for ASIP design due to its simple and regular structure, local control and communication, and high degree of modularity. This paper describes a new CFP architecture, called the wide counterflow pipeline (WCFP) that extends the original proposal to be better suited for custom embedded instruction-level parallel processors. This work presents a novel and practical application of the CFP to automatic and quick turn-around design of ASIPs. The paper introduces the WCFP architecture and describes several microarchitecture enhancements needed to get good performance from custom WCFPs. We demonstrate that custom WCFPs have performance that is up to four times better than that of ASIPs based on the original CFP.
B. R. Childers and J. W. Davidson, "Custom Wide Counterflow Pipelines for High-Performance Embedded Applications," Proceedings 2000 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00622)(PACT), Philadelphia, Pennsylvania, 2000, pp. 57.