1999 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00425) (1999)
Newport Beach, California
Oct. 12, 1999 to Oct. 16, 1999
Ramon Canal , Universitat Politecnica de Catalunya
Joan-Manuel Parcerisa , Universitat Politecnica de Catalunya
Antonio Gonzalez , Universitat Politecnica de Catalunya
In current superscalar processors, all floating-point resources are idle during the execution of integer programs. As previous works show, this problem can be alleviated if the floating-point cluster is extended to execute simple integer instructions. With minor hardware modifications to a conventional superscalar, the issue width can potentially be doubled without increasing the hardware complexity. In fact, the result is a clustered architecture with two heterogeneous clusters.In this paper we propose to extend this architecture with a dynamic steering logic that sends the instructions to either cluster. The performance of clustered architectures depends on the inter-cluster communication overhead and the workload balance. We present a scheme that uses run-time information to optimise the trade-off between these figures. The evaluation shows that this scheme can achieve an average speed-up of 35% over a conventional 8-way issue (4 int + 4 fp) machine and that it outperforms the previous proposed one.
microarchitecture, clustered architecture, cluster, code partitioning, dynamic steering, workload balance, inter-cluster communication
A. Gonzalez, R. Canal and J. Parcerisa, "A Cost-Effective Clustered Architecture," 1999 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.PR00425)(PACT), Newport Beach, California, 1999, pp. 160.