The Community for Technology Leaders
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1999)
Newport Beach, California
Oct. 12, 1999 to Oct. 16, 1999
ISSN: 1089-795X
ISBN: 0-7695-0425-6
pp: 78
Madhavi Gopal Valluri , University of Texas at Austin
R. Govindarajan , Indian Institute of Science
ABSTRACT
The phase ordering of register allocation and instruction scheduling in a compiler and their integration have been well studied for in-order issue and VLIW processors. In this paper we study this problem in the context of out-of-order issue processors. Such a study is interesting as the dynamic instruction ordering and register renaming support mechanisms in out-of-order issue processors are similar in spirit to what the complex register allocation and instruction scheduling techniques do at compile-time.We evaluated four existing techniques, namely Postpass Scheduling, Prepass Scheduling, Parallel Interference Graph, and Integrated Prepass Scheduling methods. Our initial experimental results reveal that for o-o-o issue processors the focus should be on reducing the register pressure/spill code than exposing the parallelism at compiling time.
INDEX TERMS
Instruction Scheduling, Integrated Methods, Instruction-Level Parallelism, Out-of-order Issue Processors, Register Allocation
CITATION
Madhavi Gopal Valluri, R. Govindarajan, "Evaluating Register Allocation and Instruction Scheduling Techniques in Out-Of-Order Issue Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 78, 1999, doi:10.1109/PACT.1999.807420
89 ms
(Ver 3.3 (11022016))