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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1998)
Paris, France
Oct. 12, 1998 to Oct. 18, 1998
ISSN: 1089-795X
ISBN: 0-8186-8591-3
pp: 136
Sanjeev Banerjia , North Carolina State University
Emre Ozer , North Carolina State University
Kishore N. Menezes , North Carolina State University
Sumedh W. Sathaye , North Carolina State University
Thomas M. Conte , North Carolina State University
Matthew D. Jennings , North Carolina State University
ABSTRACT
Interrupt handling in out-of-order execution processors requires complex hardware schemes to maintain the sequential state. The amount of hardware will be substantial in VLIW architectures due to the nature of issuing a very large number of instructions in each cycle. It is hard to implement precise interrupts in out-of-order execution machines, especially in VLIW processors. In this paper, we will apply the reorder buffer with future file and the history buffer methods to a VLIW platform, and present a novel scheme called the Current-state buffer, which employs modest hardware with compiler support. Unlike the other interrupt handling schemes, the Current-state buffer does not keep history state, result buffering or bypass mechanism. it is a fast interrupt handling scheme with a relatively small buffer that records the execution and exception status of operations. it is suitable for embedded processors that require a fast interrupt handling mechanism with modest hardware.
INDEX TERMS
Embedded Processors, ILP, Interrupt, Out-of-order Issue, Superscalar, VLIW.
CITATION
Sanjeev Banerjia, Emre Ozer, Kishore N. Menezes, Sumedh W. Sathaye, Thomas M. Conte, Matthew D. Jennings, "A Fast Interrupt Handling Scheme for VLIW Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 136, 1998, doi:10.1109/PACT.1998.727184
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