Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) (1998)
Oct. 12, 1998 to Oct. 18, 1998
Daniela Genius , University of Karlsruhe
Cross interference, conflicting data from several arrays, is particularly grave for caches with limited associativity. We present a uniform scheme that reduces both self and cross interference. Techniques for cyclic register allocation, namely the meeting graph, help to improve the usage of cache lines and to avoid conflicts. Cyclic graph coloring determines a new memory mapping function. Preliminary experiments show that in spite of the penalty for the more complex indexing functions, run times are improved.
cache optimization, memory mapping, cyclic graph coloring, meeting graph
D. Genius, "Handling Cross Interferences by Cyclic Cache Line Coloring," Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)(PACT), Paris, France, 1998, pp. 112.