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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1998)
Paris, France
Oct. 12, 1998 to Oct. 18, 1998
ISSN: 1089-795X
ISBN: 0-8186-8591-3
pp: 112
Daniela Genius , University of Karlsruhe
ABSTRACT
Cross interference, conflicting data from several arrays, is particularly grave for caches with limited associativity. We present a uniform scheme that reduces both self and cross interference. Techniques for cyclic register allocation, namely the meeting graph, help to improve the usage of cache lines and to avoid conflicts. Cyclic graph coloring determines a new memory mapping function. Preliminary experiments show that in spite of the penalty for the more complex indexing functions, run times are improved.
INDEX TERMS
cache optimization, memory mapping, cyclic graph coloring, meeting graph
CITATION
Daniela Genius, "Handling Cross Interferences by Cyclic Cache Line Coloring", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 112, 1998, doi:10.1109/PACT.1998.727180
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