Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192) (1998)
Oct. 12, 1998 to Oct. 18, 1998
Ireneusz Karkowski , Delft University Of Technology
Henk Corporaal , Delft University Of Technology
Due to the technological advances, mapping of embedded applications onto single-chip multi-processor systems becomes a feasible and very interesting option. What is needed is an environment that supports the designer in transforming an algorithmic specification into a suitable parallel implementation. In this paper we present the results of our experiments with one such an environment, which we developed within our laboratory. As opposed to the existing ones, our framework semi-automatically exploits different kinds of coarse and fine-grain parallelism from an embedded program written in ANSI C. It employs functional pipelining and data set partitioning simultaneously with source-to-source program transformations to obtain the most advantageous hierarchical parallelizations. This combination results in high speedups for all tested benchmarks.
heterogeneous multi-processors, application-specific architectures, compilers for parallel systems, high performance embedded system design
I. Karkowski and H. Corporaal, "Exploiting Fine- and Coarse-grain Parallelism in Embedded Programs," Proceedings. 1998 International Conference on Parallel Architectures and Compilation Techniques (Cat. No.98EX192)(PACT), Paris, France, 1998, pp. 60.