Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
Frederic Desprez , CNRS-INRIA
Jack Dongarra , CNRS-INRIA
Fabrice Rastello , CNRS-INRIA
Yves Robert , CNRS-INRIA
In the framework of fully permutable loops, tiling has been studied extensively as a source-to-source program transformation. We build upon recent results by Hogsted, Carter, and Ferrante, who aim at determining the cumulated idle time spent by all processors while executing the partitioned (tiled) computation domain. We propose new, much shorter proofs of all their results and extend these in several important directions. More precisely, we provide an accurate solution for all values of the rise parameter that relates the shape of the iteration space to that of the tiles, and for all possible distributions of the tiles to processors. In contrast, the authors deal only with a limited number of cases and provide upper bounds rather than exact formulas.
F. Desprez, Y. Robert, J. Dongarra and F. Rastello, "Determining the Idle Time of a Tiling: New Results," Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques(PACT), San Francisco, CA, 1997, pp. 307.