Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
Luis Villa , Insatituto Politecnico Nacional de Mexico D.F.
Roger Espasa , Universitat Politecnica de Catalunya--Barcelona
Mateo Valero , Universitat Politecnica de Catalunya--Barcelona
This paper presents data confirming the fact that traditional vector architectures can not reduce their vector register length without suffering a severe performance penalty. However, we will show that by combining the vector register length reduction with two different ILP techniques, decoupling and multithreading, the performance penalty can be made very small. We will show that each resulting architecture tolerates very well long memory latencies and also makes a better usage of the available storage space in each vector register. Using decoupling and short vectors, each register can be halved while still providing speedups in the range 1.04--1.49 over a traditional architecture with long registers. Using multithreading, we split a vector register file in two halfs and show that two independent threads running on such machine can yield speedups in the range 1.23--1.29 . The paper also explores configurations with 1/4 and 1/8 the original vector register size aimed at cost-conscious designs, and shows that even at 1/4 the original size, the resulting architectures can outperform a traditional machine. We also present results across a wide range of memory latencies, and show that the combination of short vectors and ILP techniques results in a very good tolerance of slow memory systems.
R. Espasa, L. Villa and M. Valero, "Effective Usage of Vector Registers in Advanced Vector Architectures," Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques(PACT), San Francisco, CA, 1997, pp. 250.