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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
ISSN: 1089-795X
ISBN: 0-8186-8090-3
pp: 236
A. Choudhary , Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA
M. Kandemir , Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA
J. Ramanujam , Dept. of Electr. Eng. & Comput. Sci., Syracuse Univ., NY, USA
ABSTRACT
Distributed memory message passing machines can deliver scalable performance but are difficult to program. Shared memory machines, on the other hand, are easier to program but obtaining scalable performance with a large number of processors is difficult. Previously, some scalable architectures based on logically-shared physically-distributed memory have been designed and implemented. While some of the performance issues like parallelism and locality are common to the different parallel architectures, issues such as data decomposition are unique to specific types of architectures. One of the most important challenges compiler writers face is to design compilation techniques that can work on a variety of architectures. In this paper, we propose an algorithm that can be employed by optimizing compilers for different types of parallel architectures. Our optimization algorithm does the following: (1) transforms loop nests such that, where possible, the outermost loops can be run in parallel across processors; (2) decomposes each array across processors; (3) optimizes interprocessor communication by vectorizing it whenever possible; and (it) optimizes locality (cache performance) by assigning appropriate storage layout for each array. Depending on the underlying hardware system, some or all of these steps can be applied in a unified framework. We present simulation results for cache miss rates, and empirical results on SUN SPARCstation 5, IBM SP-2, SGI Challenge and Convex Exemplar to validate the effectiveness of our approach on different architectures.
INDEX TERMS
parallel architectures; compiler algorithms; distributed memory machines; shared memory machines; data decomposition; optimizing compilers; parallel architectures; loop nests; interprocessor communication; cache performance; storage layout; SUN SPARCstation 5; IBM SP-2; SGI Challenge; Convex Exemplar
CITATION
A. Choudhary, M. Kandemir, J. Ramanujam, "Compiler Algorithms For Optimizing Locality And Parallelism On Shared And Distributed Memory Machines", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 236, 1997, doi:10.1109/PACT.1997.644019
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