Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
K.N. Menezes , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
S.W. Sathaye , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
T.M. Coate , Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Rapid developments in the exploitation of instruction-level parallelism are prompting deeper-pipelined, wider machines with high issue rates. Speculative execution has been used to provide the required issue bandwidth. Current methods predict a single branch at a time. Performance improvement is possible by predicting multiple branches in a single cycle. The paper presents a technique to predict paths in a single access. The correlation of a path with the branches executed before it, is exploited to provide high prediction accuracy. A novel path prediction automaton is presented The automaton is easily scalable to predict long paths through arbitrary subgraphs. It also predicts a path through a subgraph in a single access. The automaton requires only n+1 bits for predicting the 2/sup n/ paths in a subgraph of depth n. The performance of the proposed path predictor is measured. The full path accuracy (accuracy in predicting all the branches in a path) is higher than or equal to other predictors found in the literature. This performance is achieved at a low hardware cost. The scalability single access prediction and low hardware cost of the path prediction technique presented in the paper make it suitable for machines requiring high issue bandwidth.
pipeline processing; high issue-rate processors; path prediction; instruction-level parallelism; speculative execution; issue bandwidth; performance improvement; multiple branches; cycle; path prediction automaton; arbitrary subgraphs; scalability single access prediction; low hardware cost
S. Sathaye, K. Menezes and T. Coate, "Path Prediction For High Issue-Rate Processors," Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques(PACT), San Francisco, CA, 1997, pp. 178.