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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
ISSN: 1089-795X
ISBN: 0-8186-8090-3
pp: 166
Soohong P. Kim , Purdue University
Henry G. Dietz , Purdue University
Raymond R. Hoare , Purdue University
ABSTRACT
Advances in IC technology increase the integration density for higher clock rates and provide more opportunities for microprocessor design. In this paper, we propose a new paradigm to exploit instruction-level parallelism (ILP) across multiple superscalar processors on a single chip by taking advantages of both VLIW-style static scheduling techniques and dynamic scheduling of superscalar architecture. In the proposed paradigm, ILP is exploited by a compiler from a sequential program and this VLIW-like-parallelized code is further parallelized by 2-way superscalar engines at run-time. Superscalar processors are connected by an aggregate function network, which can enforce the necessary static timing constraints and provide appropriate inter-processor data communication mechanisms that are needed for ILP. The aggregate function operations are statically scheduled and implement not only fine-grain communication and control, but also simple global computations resembling systolic array operations within the network.
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CITATION
Soohong P. Kim, Henry G. Dietz, Raymond R. Hoare, "VLIW Across Multiple Superscalar Processors on a Single Chip", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 166, 1997, doi:10.1109/PACT.1997.644013
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