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Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
ISSN: 1089-795X
ISBN: 0-8186-8090-3
pp: 156
I. Karkowski , Delft Univ. of Technol., Netherlands
H. Corporaal , Delft Univ. of Technol., Netherlands
Practice shows that increasing the amount of instruction level parallelism (ILP) offered by an architecture (like adding instruction slots to VLIW instructions) does not necessary lead to significant performance gains. Instead, high hardware costs and inefficient use of this hardware may occur. Mapping embedded applications onto multiprocessor systems forms a very interesting extension to ILP. The authors describe their approach to the mapping of embedded programs written in ANSI C onto a pipeline of application specific processors. An efficient algorithm for functional pipelining of loops is presented. To validate its applicability the frequency tracking system is used as a case study. This typical embedded application is mapped onto a two-processor system delivering speedup of 1.88 in comparison with a highly optimized single core solution.
multiprocessing systems; heterogenous multiprocessor embedded system design; functional pipelining; instruction level parallelism; architecture; embedded program mapping; ANSI C program; application specific processor pipeline; efficient algorithm; loops; frequency tracking system; two-processor system; speedup; highly optimized single core solution

H. Corporaal and I. Karkowski, "Design of heterogenous multi-processor embedded systems: applying functional pipelining," Proceedings 1997 International Conference on Parallel Architectures and Compilation Techniques(PACT), San Francisco, CA, 1997, pp. 156.
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