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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
ISSN: 1089-795X
ISBN: 0-8186-8090-3
pp: 78
R. Silvera , IBM Toronto Lab.
J. Wang , Nortel Montreal Lab.
G. Gao , McGill University
R. Govindarajan , Indian Institute of Science
ABSTRACT
Several modern superscalar processors contain an out of order (OOO) instruction issue mechanism, which resolves dependencies between instructions to expose greater instruction level parallelism (ILP). How to extend a traditional instruction scheduler to take advantage of these hardware resources has presented both a challenge and an opportunity for compiler design. In this paper, we present a new approach for instruction scheduling, which reorders the instructions in a traditional instruction schedule to reduce its register pressure while maintaining the amount of ILP exploitable by the target OOO processor. This may prevent the introduction of spill code, thus producing a performance improvement. We have implemented our instruction scheduler under the MOST scheduling testbed. Our experiments show that the proposed approach reduces the register pressure by 12.81% in SPEC92 benchmark loops which do not require any spill code. For loops with a high register pressure, our approach reduced the amount of spill code required by an average of 32.08%, and produced an average performance improvement of 8.79%.
INDEX TERMS
Scheduling, Register Pressure, out-of-order issue, register renaming
CITATION
R. Silvera, J. Wang, G. Gao, R. Govindarajan, "A Register Pressure Sensitive Instruction Scheduler for Dynamic Issue Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 78, 1997, doi:10.1109/PACT.1997.644005
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