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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1997)
San Francisco, CA
Nov. 11, 1997 to Nov. 15, 1997
ISSN: 1089-795X
ISBN: 0-8186-8090-3
pp: 40
Sunil Kim , IBM, Austin, TX
Alexander V. Veidenbaum , University of Illinois at Chicago
ABSTRACT
This paper addresses the use of two latency hiding techniques, prefetching and weak consistency, for large-scale shared memory multiprocessors with compiler-controlled cache coherence management and the interaction of latency hiding techniques and network bandwidth. The performance effect of latency hiding is evaluated and compared varying the network channel bandwidth. The interaction of reads, writes, and prefetches given a limited bandwidth is studied, and an approach to better network bandwidth utilization by limiting the number of outstanding requests in each node is investigated. Increasing network (channel) bandwidth helps both prefetching and non-prefetching systems, with the initial 2x increase in bandwidth giving the most improvement. The use of prefetching can deliver a much larger improvement than increasing network bandwidth for a 128 processor system for some benchmarks, even with the minimal bandwidth. Controlling bandwidth utilization is shown to be important when prefetch and write request rates are high.
INDEX TERMS
interconnection network, weak consistency, prefetching, software cache coherence, network bandwidth, shared memory systems
CITATION
Sunil Kim, Alexander V. Veidenbaum, "The Effect of Limited Network Bandwidth and its Utilization by Latency Hiding Techniques in Large-scale Shared Memory Systems", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 40, 1997, doi:10.1109/PACT.1997.644002
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