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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Boston, MA
Oct. 20, 1996 to Oct. 23, 1996
ISBN: 0-8186-7632-9
TABLE OF CONTENTS

Foreword (PDF)

pp. ix

Reviewers (PDF)

pp. xii
Session I. Multithreaded Architectures and Compilation

Nomadic Threads: A Migrating Multithreaded Approach to Remote Memory Accesses in Multiprocessors (Abstract)

Jean-Luc Gaudiot , University of Southern California
Stephen Jenks , University of Southern California
pp. 0002

Compiling C for the EARTH Multithreaded Architecture (Abstract)

Xun Xue , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
Yingchun Zhu , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
P. Ouellet , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
G.R. Gao , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
Haiying Cai , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
L.J. Hendren , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
Xinan Tang , Sch. of Comput. Sci., McGill Univ., Montreal, Que., Canada
pp. 0012
Session II. Forecasting Branches and Memory Access

The Effects of Mispredicted-Path Execution on Branch Prediction Structures (Abstract)

Jared Stark , The University of Michigan
Tse-Hao Hsing , The University of Michigan
Stephan Jourdan , Universite Paul Sabatier
Yale N. Patt , The University of Michigan
pp. 0058

Improving the Effectiveness of Software Prefetching with Adaptive Execution (Abstract)

Daeyeon Park , University of Southern California
Rafael H. Saavedra , University of Southern California
pp. 0068
Session III. New Techniques in Instruction-Level Parallelism

Swing Modulo Scheduling: A Lifetime-Sensitive Approach (Abstract)

Josep Llosa , Universitat Politecnica de Catalunya
pp. 0080

An Efficient Global Resource-Directed Approach to Exploiting Instruction-Level Parallelism (Abstract)

Alexandru Nicolau , University of California,Irvine
Steven Novack , University of California,Irvine
pp. 0087

The Design of a Modulo Scheduler for a Superscalar RISC Processor (Abstract)

P. Tinumalai , Sun Microsystems Inc., Mountain View, CA, USA
K. Subramanian , Sun Microsystems Inc., Mountain View, CA, USA
B. Beylin , Sun Microsystems Inc., Mountain View, CA, USA
pp. 0097
Session IV. Short Papers and Posters

Multithread Execution Mechanisms on RICA-1 for Massively Parallel Computation (Abstract)

S. Sakai , RWC Tsukuba Res. Center, Ibaraki, Japan
H. Matsuoka , RWC Tsukuba Res. Center, Ibaraki, Japan
H. Hirono , RWC Tsukuba Res. Center, Ibaraki, Japan
K. Okamato , RWC Tsukuba Res. Center, Ibaraki, Japan
T. Yokota , RWC Tsukuba Res. Center, Ibaraki, Japan
pp. 0116

I-Structure Software Cache: A Split-Phase Transaction Runtime Cache System (Abstract)

Wen-Yen Lin , University of Southern California
Jean-Luc Gaudiot , University of Southern California
pp. 0122

A Heuristic Approach for Finding a Solution to the Constant-Degree Parallelism Alignment Problem (Abstract)

Marc Gengler , Ecole Normale Suprieure de Lyon
Claude G. Diderich , Swiss Federal Institute of Technolog
pp. 0127

Identifying the Capability of Overlapping Computation with Communication (Abstract)

H. Sakane , Electrotechnical Laboratory
H. Yamana , Electrotechnical Laboratory
M. Sato , Electrotechnical Laboratory
Y. Yamaguchi , Electrotechnical Laboratory
J. Ku , New Jersey Institute of Technology
S. Sakai , Electrotechnical Laboratory
Y. Kodama , Electrotechnical Laboratory
A. Sohn , New Jersey Institute of Technology
pp. 0133

Elastic-Plastic Flow Simulation Using the Supercomputer Toolkit (Abstract)

A. Goikhman , Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
J. Katzenelson , Dept. of Electr. Eng., Technion-Israel Inst. of Technol., Haifa, Israel
pp. 0144

Managing the Computing Space in the mpC Compiler (Abstract)

Alexey Kalinov , Russian Academy of Sciences
Dmitry Arapov , Russian Academy of Sciences
Alexey Lastovetsky , Russian Academy of Sciences
pp. 0150

A Fine-Grain Multithreading Superscalar Architecture (Abstract)

Mat Loikkanen , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
pp. 0163

Branch Prediction and Simultaneous Multithreading (Abstract)

A. Seznec , IRISA, Rennes, France
S. Hily , IRISA, Rennes, France
pp. 0169

A Compiler Transformation to Improve Memory Access Time in SIMD Systems (Abstract)

H. Abu-Haimed , Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
L. Bic , Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
M. Al-Mouhamed , Dept. of Comput. Eng., King Fahd Univ. of Pet. & Miner., Dhahran, Saudi Arabia
pp. 0174

A Scalable Register File Architecture for Dynamically Scheduled Processors (Abstract)

Steven Wallace , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
pp. 0179
Session V. Applications and Tools

Dynamic Parallelization of Modifications to Directed Acyclic Graphs (Abstract)

Lorenz Huelsbergen , Bell Laboratories Lucent Technologies
pp. 0186

Performance Tuning Scientific Codes for Dataflow Execution (Abstract)

R. Arvind , Massachusetts Institute of Technology
Paul Johnson , Massachusetts Institute of Technology
Andrew Shaw , Massachusetts Institute of Technology
pp. 0198

Implementation Techniques for a Parallel Relative Debugger (Abstract)

C. Watson , Sch. of Comput. & Inf. Technol., Griffith Univ., Brisbane, Qld., Australia
D. Abramson , Sch. of Comput. & Inf. Technol., Griffith Univ., Brisbane, Qld., Australia
R. Sosic , Sch. of Comput. & Inf. Technol., Griffith Univ., Brisbane, Qld., Australia
pp. 0218
Session VI. Compiler Techniques and Memory Hierarchies

Loop Induction Variable Canonicalization in Parallelizing Compilers (Abstract)

Shin-Ming Liu , Silicon Graphics Computer Systems
Fred Chow , Silicon Graphics Computer Systems
Raymond Lo , Silicon Graphics Computer Systems
pp. 0228

Combining Optimization for Cache and Instruction-Level Parallelism (Abstract)

Steve Carr , Michigan Technological University
pp. 0238

A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems (Abstract)

R.W. Ford , University of Manchester
A.P. Nisbet , University of Manchester
pp. 0248
Session VIII. Automatic Parallelization and Applications

Adaptive Granularity: Transparent Integration of Fine- and Coarse-Grain Communications (Abstract)

Daeyeon Park , University of Southern California
Rafael H. Saavedra , University of Southern California
pp. 0260

Optimal Fine and Medium Grain Parallelism Detection in Polyhedral Reduced Dependence Graphs (Abstract)

F. Vivien , Lab. LIP, Ecole Normale Superieure de Lyon, France
A. Darte , Lab. LIP, Ecole Normale Superieure de Lyon, France
pp. 0281

The Compiler TwoL for the Design of Parallel Implementations (Abstract)

Thomas Rauber , Universitaet des Saarlandes
Gudula Ruenger , Universitaet des Saarlandes
pp. 0292

Author Index (PDF)

pp. 0303
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