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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Boston, MA
Oct. 20, 1996 to Oct. 23, 1996
ISBN: 0-8186-7632-9
pp: 0248
A.P. Nisbet , University of Manchester
R.W. Ford , University of Manchester
ABSTRACT
This paper presents a new compiler algorithm to eliminate invalidation traffic in virtual shared memory using a hybrid distributed invalidation scheme. It aggressively exploits static scheduling and data layout to accurately determine only those instances when invalidation is necessary, thus avoiding the additional read misses of previous schemes. Equations determining precisely what data should be invalidated are presented and followed by the derivation of approximations amenable to compiler manipulation. Compiler-directed invalidation in the presence of arbitrary control-flow is described and the definition of a compiler algorithm is presented. Preliminary experimental results on three programs show that this analysis can drastically reduce the amount of invalidation traffic and write misses.
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CITATION
M.F.P. O'Boyle, A.P. Nisbet, R.W. Ford, "A Compiler Algorithm to Reduce Invalidation Latency in Virtual Shared Memory Systems", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0248, 1996, doi:10.1109/PACT.1996.552673
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