The Community for Technology Leaders
Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Boston, MA
Oct. 20, 1996 to Oct. 23, 1996
ISBN: 0-8186-7632-9
pp: 0228
Shin-Ming Liu , Silicon Graphics Computer Systems
Fred Chow , Silicon Graphics Computer Systems
Raymond Lo , Silicon Graphics Computer Systems
ABSTRACT
Loop induction variable canonicalization transforms a loop to use a single primary induction variable that is incremented by one at the end of each iteration. In this process, other induction variables in the loop, called secondary induction variables, are removed from the loop, with their original references expressed in terms of the primary induction variable, and their loop exit values assigned to them after the loop exit. This paper presents a simple and powerful approach to loop induction variable canonicalization in which the problem is broken up into a sequence of steps. The whole canonicalization process is integrated into a global optimizer that builds an SSA representation of the program, performs global optimizations and hands the optimized code on to other components in the compiler that perform loop and instruction level parallelization. By taking advantage of optimizations that will be performed later, each step in the canonicalization process can be made small and efficient. By letting generic parts of the optimizer share in the work, the approach infuses generality into the solution and provides automatic coverage of a wide variety of forms of induction variable occurrences. A number of examples are given to show the effectiveness of the approach. We also provide a set of measurements that shows that the additional compile-time cost incurred due to implementing our approach is small.
INDEX TERMS
Copy Propagation, Dead Store Elimination, Induction Variable Expansion, Induction Variable Recog nition
CITATION
Shin-Ming Liu, Fred Chow, Raymond Lo, "Loop Induction Variable Canonicalization in Parallelizing Compilers", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0228, 1996, doi:10.1109/PACT.1996.554033
88 ms
(Ver 3.3 (11022016))