Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Oct. 20, 1996 to Oct. 23, 1996
Steven Wallace , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
A major obstacle in designing dynamically scheduled processors is the size and port requirement of the register file. By using a multiple banked register file and performing dynamic result renaming, a scalable register file architecture can be implemented without performance degradation. In addition, a new hybrid register renaming technique to efficiently map the logical to physical registers and reduce the branch misprediction penalty is introduced. The performance was simulated using the SPEC95 benchmark suite.
Steven Wallace, Nader Bagherzadeh, "A Scalable Register File Architecture for Dynamically Scheduled Processors", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0179, 1996, doi:10.1109/PACT.1996.552666