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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Boston, MA
Oct. 20, 1996 to Oct. 23, 1996
ISBN: 0-8186-7632-9
pp: 0163
Mat Loikkanen , University of California, Irvine
Nader Bagherzadeh , University of California, Irvine
ABSTRACT
In this study we show that fine-grain multithreading is an effective way to increase instruction-level parallelism and hide the latencies of long-latency operations in a superscalar processor. The effects of long-latency operations, such as remote memory references, cache-misses, and multi-cycle floating-point calculations, are detrimental to performance since such operations typically cause a stall. Even superscalar processors, that are capable of performing various operations in parallel, are vulnerable. A fine-grain multithreading paradigm and unique multithreaded superscalar architecture is presented. Simulation results show significant speedup over single-threaded superscalar execution.
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CITATION
Mat Loikkanen, Nader Bagherzadeh, "A Fine-Grain Multithreading Superscalar Architecture", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0163, 1996, doi:10.1109/PACT.1996.552663
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