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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Boston, MA
Oct. 20, 1996 to Oct. 23, 1996
ISBN: 0-8186-7632-9
pp: 0116
K. Okamato , RWC Tsukuba Res. Center, Ibaraki, Japan
S. Sakai , RWC Tsukuba Res. Center, Ibaraki, Japan
H. Matsuoka , RWC Tsukuba Res. Center, Ibaraki, Japan
T. Yokota , RWC Tsukuba Res. Center, Ibaraki, Japan
H. Hirono , RWC Tsukuba Res. Center, Ibaraki, Japan
ABSTRACT
Abstract: This paper presents a multithreaded processor architecture for massively parallel computers, and presents RICA-1 multithreaded processor based on it. RICA-1 provides fairly efficient mechanisms of message reception, thread invocation, message generation/transmission and synchronization. It provides simple communication pipelines. Computation pipelines and communication pipelines are highly fused within a processor architecture. Parallel primitives such as remote memory access, remote procedure call and synchronizations are efficiently performed by RICA-1. The first version of RICA-1 is being implemented by a CMOS standard cell chip with 200 K random gates and 13 KB internal RAMs. It is packed into the 527 pin CPGA package and will operate with a 50 MHz clock in August 1996. In RICA-1, communication pipelines and the RISC-type execution pipelines are highly fused by a simple sequencer and three sets of register files substantially reduces the thread switch overhead.
INDEX TERMS
multiprogramming; multithread execution mechanisms; RICA-1; massively parallel computation; multithreaded processor architecture; RISC; message reception; thread invocation; message generation; message transmission; synchronization; communication pipelines; computation pipelines; register files; remote memory access; remote procedure call; thread switch overhead; CMOS; random gates; internal RAM; CPGA package; clock; 13 KB; 50 MHz
CITATION
K. Okamato, S. Sakai, H. Matsuoka, T. Yokota, H. Hirono, "Multithread Execution Mechanisms on RICA-1 for Massively Parallel Computation", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0116, 1996, doi:10.1109/PACT.1996.552653
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