Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Oct. 20, 1996 to Oct. 23, 1996
Today's deeply pipelined, superscalar processors rely on accurate branch prediction in order to approach their performance potential. Branch mispredictions result in a flushing of the speculative information in the pipeline, thus limiting the amount of useful work that can be done. The 2-level branch predictors have been shown to achieve high prediction accuracy. However, it has also been shown that there is a high degree of pattern history table interference in 2-level branch predictors and that the interference generally has a negative effect on the prediction accuracy. This paper introduces a method for reducing the pattern history table interference by dynamically identifying some easily predictable branches and inhibiting the pattern history table update for these branches. We show how this technique reduces pattern history table interference for two versions of the 2-level branch predictor and that this significantly improves branch prediction accuracy for the SPEC 95 benchmarks. In particular, we eliminate up to 30% of the mispredictions for the gcc benchmark.
M. Evers, P. Chang and Y. N. Patt, "Improving Branch Prediction Accuracy by Reducing Pattern History Table Interference," Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques(PACT), Boston, MA, 1996, pp. 0048.