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Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques (1996)
Boston, MA
Oct. 20, 1996 to Oct. 23, 1996
ISBN: 0-8186-7632-9
pp: 0024
ABSTRACT
This paper presents performance and step-by-step complexity analysis of two different design alternatives of multithreaded architecture: dynamic inter-thread resource scheduling and static resource allocation. We show that with two concurrent threads the dynamic scheduling processor achieves from 5 to 45% higher performance at the cost of much more complicated design. The paper shows that for a relatively high number of execution resources the complexity of the dynamic scheduling logic will inevitably require design compromises. Moreover, high chip-wide communication time and an "incomplete bypassing network" will force the dynamic scheduling to use static-like execution unit assignment, thus reducing its performance advantage. At the same transistor budget the static architecture may implement additional functional units, resulting in better overall performance.
INDEX TERMS
multithreaded architecture, hardware complexity, ILP, performance evaluation
CITATION
Michael Bekerman, Avi Mendelson, Gad Sheaffer, "Performance and Hardware Complexity Tradeoffs in Designing Multithreaded Architectures", Proceedings of the 22nd International Conference on Parallel Architectures and Compilation Techniques, vol. 00, no. , pp. 0024, 1996, doi:10.1109/PACT.1996.552552
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