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Pacific-Asia Workshop on Computational Intelligence and Industrial Application, IEEE (2008)
Dec. 19, 2008 to Dec. 20, 2008
ISBN: 978-0-7695-3490-9
pp: 700-703
In this paper, a decoding IP core for Audio Video Coding Standard (AVS) was designed, which can support AVS JiZhun profile High-Definition video bit stream real-time decoding. System composing of the SOC design and control flow of decoding was described in detail. Logical and feasible division between software and hardware was presented on the basis of sufficient validity check. C reference model for whole decoder was proposed as well, which was used to verify the decoding algorithm. Clear and smooth picture can be output both on the C model environment and SOC platform. Besides, system clock supply for IP core and sub-modules inside can be halted whenever necessary, so that power consumption for the whole system was also reduced. Though designed for AVS originally, the proposed architecture can be adapted to other coding standards easily.
AVS, C model, IP core, SOC

L. Wei, "A SOC Design for AVS Video Decoding," 2008 Pacific-Asia Workshop on Computational Intelligence and Industrial Application. PACIIA 2008(PACIIA), Wuhan, 2008, pp. 700-703.
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