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Circuits, Communications and Systems, Pacific-Asia Conference on (2009)
Chengdu, China
May 16, 2009 to May 17, 2009
ISBN: 978-0-7695-3614-9
pp: 602-605
ABSTRACT
This Paper presents the realization of a simple but efficient technique to increase the performance of the processor simulator, which can be used both for software performance evaluation or hardware performance evaluation, such as MPSoC. Due to the fast increasing of the software complexity, it brings forward more requirements on the speed of the processor simulation, which simulates a certain target processor (such as PowerPC, ARM etc.) on certain host platform (usually PC ). The performance improvement of a processor simulator can enlarge the exploration space and shorten the time-to-market. The existing approaches use either interpretive simulator or complied simulator or a binary translator. This paper performs binary to C translation to generate the processor simulator.
INDEX TERMS
compiled simulator, binary to C translation, MPSoC
CITATION

K. Wang, W. Shu and B. Xiao, "A Framework for Software Performance Simulation Using Binary to C Translation," 2009 Pacific-Asia Conference on Circuits, Communications and Systems (PACCS 2009)(PACCS), Chengdu, 2009, pp. 602-605.
doi:10.1109/PACCS.2009.57
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