Circuits, Communications and Systems, Pacific-Asia Conference on (2009)
May 16, 2009 to May 17, 2009
A 32 X 32 register file based on dual transmission gate adiabatic logic (DTGAL) is implemented with TSMC 0.18mm process. The energy of all nodes with large capacitances including storage cells can be well recovered without non-adiabatic loss. Full-custom layouts are drawn. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the adiabatic register file can work very well.
memory, low power, energy recovery
J. Hu, L. Yu and L. Li, "Low-Power Register File Using N-type and P-type Adiabatic Logic Circuits," 2009 Pacific-Asia Conference on Circuits, Communications and Systems (PACCS 2009)(PACCS), Chengdu, 2009, pp. 342-345.