Circuits, Communications and Systems, Pacific-Asia Conference on (2009)
May 16, 2009 to May 17, 2009
This paper focuses on the full-custom layout implementation of the single-phase power-gating adiabatic circuits. A transmission gate is used as the power-gating switch, and the power-gated adiabatic logic block uses the CAL (Clocked Adiabatic Logic) circuits. A power-gating 8-bit full adder based on improved CAL circuits is verified. For a comparison, an 8-bit full adder based on improved CAL circuits without power-gating has also been drawn. All circuits are implemented with TSMC 0.18um process. The energy and functional simulations have been performed using the net-list extracted from their layouts. The results show the improved CAL 8-bit full adder with the power-gating scheme can work very well, and it attains more than 36.2% power reductions than the 8-bit full adder without power-gating at 100 MHz when active is 0.2.
single-phase adiabatic circuits, low power, power-gating, physical layouts
J. Fu, X. Luo and J. Hu, "The Implementation of Single-Phase Power-Gating Adiabatic Circuits Using Improved CAL Circuits," 2009 Pacific-Asia Conference on Circuits, Communications and Systems (PACCS 2009)(PACCS), Chengdu, 2009, pp. 334-337.