Circuits, Communications and Systems, Pacific-Asia Conference on (2009)
May 16, 2009 to May 17, 2009
A 10-bit 3Ms/s 90nm CMOS SAR A/D converter is presented in this paper. Pseudo-differential comparison architecture is utilized to improve the performance, where the errors caused by clock feed-through and charge injection can be considered as common-mode interferences. Instead of traditional voltage scaling architecture, an R-C combination based D/A converter is used to reduce the chip area. And due to the inherent S/H function of its capacitor array, no additional S/H circuit is needed. To achieve good matching performance, each unit resistor is sided by dummies and the capacitors are routed with a common-central symmetry method. This converter fabricated in SMIC 90nm CMOS process occupies an area of 217um×220um. With a 3.3V analog supply and a 1.0V digital supply, the measured DNL and INL are 0.33LSB and 0.74LSB respectively. With a 2.7MHz input signal sampled at 3Ms/s, the power dissipation is measured to be 12.08mW and the SFDR and ENOB are 62.97dB and 9.38Bits respectively.
SAR A/D converter, pseudo-differential architecture, R-C combination based D/A converter, inherent S/H function, good matching performance
Y. Yang, Y. Xiao, Z. Zhu, J. Chen and X. Tong, "A Novel R-C Combination Based Pseudo-differential SAR A/D Converter in 90nm CMOS Process," 2009 Pacific-Asia Conference on Circuits, Communications and Systems (PACCS 2009)(PACCS), Chengdu, 2009, pp. 289-292.