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Circuits, Communications and Systems, Pacific-Asia Conference on (2009)
Chengdu, China
May 16, 2009 to May 17, 2009
ISBN: 978-0-7695-3614-9
pp: 265-268
A novel globally asynchronous locally synchronous delay insensitive self-timed wrapper for network on chips is presented. To prevent the occurrence of data sampling error, the wrapper detects the read/write signal and controls the stoppable clock module to stop the clock when data come. Sender wrapper and receiver wrapper consist of C element and Null convention logic, and NULL signals can be inserted into output data automatically in order to guarantee the characteristics of on-chip delay insensitive. The wrapper resolves the work of delay matching and data loss issues in traditional bundled data protocol wrapper. Simulations under different fabrication variations are implemented based on SMIC 0.18μm CMOS technology. Sender wrapper and receiver wrapper allow synchronous modules work at speed of 2.87GHz and2.59GHz respectively with average dynamic power dissipation of 828.2μW and 819.8μW. Its advantages of high-speed low-power, delay-insensitive and no data losses make it a viable option for high-performance high-robustness interconnection of network-on-chip.
network on chips, GALS, dual-rail protocol, asynchronous circuit, high-speed low-power

Z. Zhu, X. Guan, Y. Yang and D. Zhou, "A GALS Delay-insensitive Self-timed Wrapper for Network on Chips," 2009 Pacific-Asia Conference on Circuits, Communications and Systems (PACCS 2009)(PACCS), Chengdu, 2009, pp. 265-268.
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